LDMOS in SOI technology with very-thin silicon film

Extended-$\hbox{p}^{+}$ Stepped Gate LDMOS for Improved Performance

“…1. The conventional LDMOS structure used in our simulation is similar to the structure proposed by [6] and has a field plate over the drift region to enhance the high-voltage capabilities as shown in Fig. 1(a) [12].…”

“…In the recent past, developing high voltage thin film LDMOS has gained importance due to the possibility of its integration with low power CMOS devices and heterogeneous microsystems [6]. But realization of high voltage devices in thin film SOI is challenging because floating body effects affect the breakdown characteristics.…”

“…Another problem with the thin film SOI LDMOS is the kink appearing in the output characteristics. Though the kink can be eliminated by reducing the drift region doping concentration, the increased drift region resistance degrades the other device parameters [6]. Therefore, the motivation of this work is to explore structural modifications in SOI LDMOS to enhance its high voltage capabilities.…”

A new technique in LDMOS transistors to improve the breakdown voltage and the lattice temperature

“…Also, the design of buried oxide (BOX) has been paid considerable attention in the SOI power device to improve the blocking voltage [1][2][3], because the SOI LDMOS suffers from low vertical breakdown voltage (BV) and limited thicknesses of top silicon layer and the BOX. These conditions make a lot of problems in such devices [4][5][6].…”

Dual Ground Plane EDMOS in 28nm FDSOI for 5V power management applications

“…Despite these promising advantages, no work has been reported to date on HVMOS in UTBB or in ultrathin SOI with silicon film and buried oxide respectively thinner than T SI = 70 nm and T BOX = 145 nm [8][9][10]. Earlier studies and analytical models of ultra-thin SOI high-voltage devices [11][12][13] reveal that in thin silicon film structures the breakdown voltage is limited by T SI and T BOX .…”