Extended-$\hbox{p}^{+}$ Stepped Gate LDMOS for Improved Performance

Abstract

Abstract-In this paper, we propose a new Extended-p + Stepped Gate (ESG) thin film SOI LDMOS with an extended-p + region beneath the source and a stepped gate structure in the drift region of the LDMOS. The hole current generated due to impact ionization is now collected from an n + p + junction instead of an n + p junction thus delaying the parasitic BJT action. The stepped gate structure enhances RESURF in the drift region, and minimizes the gate-drain capacitance. Based on twodimensional simulation results, we show that the ESG LDMOS exhibits approximately 63% improvement in breakdown voltage, 38% improvement in on-resistance, 11% improvement in peak transconductance, 18% improvement in switching speed and 63% reduction in gate-drain charge density compared with the conventional LDMOS with a field plate.

A Review of Super Junction LDMOS

“…SOI-LDMOS has better performance than LDMOS on bulk silicon [25][26], so the SJ-LDMOS on SOI material has been investigated in recent years. Figure 12 shows USJ-LDMOS on SOI [27].…”

Investigation of laterally single-diffused metal oxide semiconductor (LSMOS) field effect transistor

“…Laterally single diffused metal-oxide-semiconductor (LDMOS) field effect transistor (FET) is popularly used in automotive applications, flat panel displays, high voltage ICs, power management ICs, RADAR, motor drives, switching applications and power amplifiers [1][2][3][4][5][6][7]. Its fabrication is compatible with the standard CMOS process line and can be implemented with SOI technology for improved performance.…”

A 100-V High-Performance SOI Trench LDMOS with Low Cell Pitch

“…Table I presents the optimized values of the device parameters used in the simulation for both structures to obtain V br of 103 V. For the TLDMOS structure, the oxide thickness (t ox1 ) between the vertical field plate and the drift region is a critical dimension affecting the breakdown voltage and on-resistance. 9 The value of t ox1 was varied from 30 nm to 180 nm to determine its effect on the overall performance of the device. It is noteworthy that, for t ox1 equal to the gate oxide (30 nm), the fabrication process is relatively easy to realize; however, this would degrade the performance of the device.…”