Investigation of Single Event Induced Soft Errors in Programmable Metallization Cell Memory

Mahalanabis, D.; Barnaby, Hugh; Kozicki, Michael; Bharadwaj, Vineeth; Rajabi, Saba

doi:10.1109/tns.2014.2358235

Cited by 19 publications

(15 citation statements)

References 20 publications

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“…SBU in the CBRAM cell is possible, consistent with previous studies on test structures [16], [17]. However there are key distinctions for the SBU observed here.…”

Section: Single Event Upsetsupporting

confidence: 92%

Single-Event Effect Performance of a Conductive-Bridge Memory EEPROM

Chen

Wilcox

Berg

et al. 2015

IEEE Trans. Nucl. Sci.

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Conductive-bridge random access memory (CBRAM) is a programmable metallization cell (PMC) memory in the family of resistive memories [1]−[4]. The scaling limitations of flash spurred the introduction of alternative non-volatile memory technologies. The CBRAM has shown advantages in performance and scalability relative to other alternative non-volatile memory technologies [2]. Additionally, the resistive elements can be fabricated back-end-of-line (BEOL) on CMOS processes [1]. Therefore, it can be more easily integrated into existing CMOS wafer fabrication lines. The rapid development in resistive memories has expedited the release of commercial-ready products. The CBRAM from Adesto Technologies is an electrically erasable programmable read-only memory (EEPROM) [1], [4]−[5].The CBRAM offers a promising alternative to traditional chargetrap or floating-gate technologies for space applications, due to its intrinsic radiation tolerance. Previous studies found that the Adesto CBRAM EEPROM is error free up to 450 krad(GeS 2 ) of gamma rays, and up to 3 Mrad(CaF 2 ) of 10 keV x-rays [13]−[14]. The device is also hardened against displacement damage up to 10 14 n/cm 2 of 1 MeV equivalent neutrons [14]. Other studies suggest that single-event upset (SEU) at the cell level can occur, due to upset of the access transistor [16]−[17]. We previously investigated the SEE performance of a microcontroller with embedded reduction-oxidation memory [15]. There is yet to be a comprehensive SEE evaluation of a stand-alone resistive memory product. Here, we investigate the SEE susceptibility of a commercial EEPROM, the first stand-alone memory based on CBRAM technology.

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“…SBU in the CBRAM cell is possible, consistent with previous studies on test structures [16], [17]. However there are key distinctions for the SBU observed here.…”

Section: Single Event Upsetsupporting

confidence: 92%

Single-Event Effect Performance of a Conductive-Bridge Memory EEPROM

Chen

Wilcox

Berg

et al. 2015

IEEE Trans. Nucl. Sci.

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“…Initial heavy-ion studies revealed that in a 1T1R Ag/GeS 2 cell, bit flips occur when the high-resistance state experiences a resistance decreases [129], similar to that observed in ReRAM by Bennett et al [114]. This is attributed to current resulting from an ion striking drain of the select transistor.…”

Section: Conducting Bridge Ramsupporting

confidence: 53%

Radiation Effects in Advanced and Emerging Nonvolatile Memories

Marinella

2021

IEEE Trans. Nucl. Sci.

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Despite hitting major roadblocks in 2-D scaling, NAND flash continues to scale in the vertical direction and dominate the commercial nonvolatile memory market. However, several emerging nonvolatile technologies are under development by major commercial foundries or are already in small volume production, motivated by storage-class memory and embedded application drivers. These include spin-transfer torque magnetic random access memory (STT-MRAM), resistive random access memory (ReRAM), phase change random access memory (PCRAM), and conductive bridge random access memory (CBRAM). Emerging memories have improved resilience to radiation effects compared to flash, which is based on storing charge, and hence may offer an expanded selection from which radiation-tolerant system designers can choose from in the future. This review discusses the material and device physics, fabrication, operational principles, and commercial status of scaled 2-D flash, 3-D flash, and emerging memory technologies. Radiation effects relevant to each of these memories are described, including the physics of and errors caused by total ionizing dose, displacement damage, and single-event effects, with an eye toward the future role of emerging technologies in radiation environments.

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“…Similar to other memory technologies [10], memristors are vulnerable to soft errors (unintentional temporary changes in logical state). Causes for these errors include diffusion of oxygen vacancies (leading to state drift) [6], ion strikes [7], [8], and environmental factors [9]. These soft errors can accumulate over time [6], [7], [15] or occur abruptly [8], [9].…”

Section: B Soft Errors In Memristorsmentioning

confidence: 99%

“…Memristors are vulnerable to soft errors originating from the diffusion of oxygen vacancies (leading to state drift) [6], ion strikes [7], [8], and environmental factors [9]. Memristive PIM solutions are vulnerable since soft errors may change the operands of subsequent computations undetected (leading to incorrect results and wasted time/energy).…”

Section: Introductionmentioning

confidence: 99%

Efficient Error-Correcting-Code Mechanism for High-Throughput Memristive Processing-in-Memory

Leitersdorf¹,

Perach²,

Ronen³

et al. 2021

Preprint

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Inefficient data transfer between computation and memory inspired emerging processing-in-memory (PIM) technologies. Many PIM solutions enable storage and processing using memristors in a crossbar-array structure, with techniques such as memristor-aided logic (MAGIC) used for computation. This approach provides highly-paralleled logic computation with minimal data movement. However, memristors are vulnerable to soft errors and standard error-correcting-code (ECC) techniques are difficult to implement without moving data outside the memory. We propose a novel technique for efficient ECC implementation along diagonals to support reliable computation inside the memory without explicitly reading the data. Our evaluation demonstrates an improvement of over eight orders of magnitude in reliability (mean time to failure) for an increase of about 26% in computation latency.

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Investigation of Single Event Induced Soft Errors in Programmable Metallization Cell Memory

Cited by 19 publications

References 20 publications

Single-Event Effect Performance of a Conductive-Bridge Memory EEPROM

Single-Event Effect Performance of a Conductive-Bridge Memory EEPROM

Radiation Effects in Advanced and Emerging Nonvolatile Memories

Efficient Error-Correcting-Code Mechanism for High-Throughput Memristive Processing-in-Memory

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