NAND Flash memories are currently the dominant mass storage technology in the commercial market, and they are finding their way into space systems thanks to the technology's high density and low cost [1]. NASA and other government agencies as well as academia have actively investigated the radiation susceptibility of each generation of NAND flash from various commercial vendors, including the Micron and Samsung [2]−[4]. The growing complexity of the device's control circuits as well as the continued shrinking of the memory cell area have introduced new challenges for radiation testing. Existing single-event effect (SEE) test standards include the JESD57, ASTM F1192, and ESCC No. 25100 [5]−[7]. These test standards provide top level guidance for single-event testing in general. NASA has recently published a more detailed test guideline targeted specifically at current nonvolatile memories [8]. However, the current test methodologies need to be continuously updated with test findings.For example, the traditional test protocols are predicated on the assumption that the SEE cross section remains constant with fluence. So the device upset rate in space is constant over time. Therefore, typical heavy ion tests demand a fluence high enough to cover a representative portion of the device sensitive regions. In this investigation, we observed the cross section varies inversely with the test fluence, which we attribute to the range of upset sensitivities of the memory cells.

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Single-event effect (SEE) and total ionizing dose (TID) test results are presented for various hardened and commercial power metal-oxide-semiconductor field effect transistors (MOSFETs), including vertical planar, trench, superjunction, and lateral process designs. Index Terms-power MOSFET, single-event effect (SEE), single-event gate rupture (SEGR), single-event burnout (SEB), total ionizing dose (TID) I. INTRODUCTION OWER MOSFETs continue to be used ubiquitously in spacecraft. Several topologies are available. Planar, vertical double-diffused MOSFET (VDMOS) structures (Fig. 1A) have long dominated the radiation-hardened offerings, and the number of manufacturers providing hardened VDMOS has recently expanded. Commercially, vertical trench-gate style MOSFETs (Fig. 1B) have been a staple for low-to medium-voltage applications due to their lower on-state resistance (R DS_ON). The vertically-oriented gates penetrate past the body region thereby eliminating the parasitic junction field effect transistor (JFET) that limits the minimum cell pitch in planar VDMOS. For higher-voltage power MOSFETs, a lower R DS_ON has been achieved through development of the superjunction structure (Fig. 1C). Superjunction power MOSFETs (SJ MOSFETs) have charge-compensating columns within the epilayer that permit a shallower drift region for a given breakdown voltage (BV DSS). Radiationhardened SJ MOSFETs have just become available in the past year and hardened trench-style MOSFETs are in development.