Investigation of the wideband operation capability of Gilbert cell mixers

Cabuk, Alper; Yeo, Kiat Seng; G., J.; A., M.

doi:10.1002/mop.10237

Cited by 2 publications

(1 citation statement)

References 9 publications

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“…Finally, the IF output voltage is created due to the current through the load resistors ( R L 1 ). The selected mixer topology is the double‐balanced configuration known as the Gilbert cell (see Fig. ).…”

Section: Circuits Analysismentioning

confidence: 99%

A low‐power RF receiver for digital TV DVB‐SH

García-Vázquez

Khemchandani

Pino

2014

Micro & Optical Tech Letters

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This article describes a low‐power RF front‐end for digital video broadcasting–satellite services to handhelds (2.17–2.2 GHz) implemented in UMC CMOS 90‐nm process. This receiver includes a resistive feedback low‐noise amplifier and a double‐balanced Gilbert mixer. Measurements show a conversion gain of 24.1 dB, a 3‐dB noise figure, an input return loss of −11.9 dB, and an output compression point of −2.2 dBm. This combination draws 12.4 mW from a 1.2 V supply. © 2014 Wiley Periodicals, Inc. Microwave Opt Technol Lett 56:528–531, 2014

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Section: Circuits Analysismentioning

confidence: 99%

A low‐power RF receiver for digital TV DVB‐SH

García-Vázquez

Khemchandani

Pino

2014

Micro & Optical Tech Letters

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Design of high-speed low-power clock and data recovery circuit

Cabuk¹

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In this thesis, the design of fully integrated high-speed low-power clock and data recovery (CDR) circuits in complementary metal-oxide-semiconductor (CMOS) devices for synchronous optical network (SONET) applications has been explored. The majority of the backbone optical communication systems are based on the SONET standards. The "SONET OC-192 Specifications" have been defined for 10-Gb/s optical communication applications in order to evaluate the jitter performance of the designs. Despite the aggressive device scaling in CMOS technology, the CDR circuits that are realized in CMOS processes still face significant high-frequency design and speed constraints. When it comes to complying with the stringent jitter requirements posed by the OC-192 standards, CMOS circuits have to work harder than their GaAs or SiGe counterparts to overcome the limitations due to the high-frequency parasitics. Extensive research work must be carried out at all fronts related to the CMOS CDRs in order to obtain a total solution to the problems currently faced by the designers. To contribute to the pool of these solutions, we have proposed several modifications and methods in this thesis. Before going into the detailed discussion, we should note that all the design work presented here is done on the phase-locked loop (PLL)-based CDR architectures and their building blocks.

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Investigation of the wideband operation capability of Gilbert cell mixers

Abstract: also affected. Equation (10) shows that only the imaginary part of changes sign, if the signs of the real parts of both the permittivity and the permeability are altered.Suppose two ICMs labeled p and q possess identical response properties at a certain frequency-except that 0

Cited by 2 publications

References 9 publications

A low‐power RF receiver for digital TV DVB‐SH

A low‐power RF receiver for digital TV DVB‐SH

Design of high-speed low-power clock and data recovery circuit

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