Investigation on Cu TSV-Induced KOZ in Silicon Chips: Simulations and Experiments

Tsai, Ming-Yi; Huang, P. S.; Huang, Chenyu; Jao, Hsiu; Huang, Brady; Wu, Blacksmith; Lin, Yuanyuan; Liao, Will; Huang, Joe; Huang, Lawrence; Shih, Steven; Lin, Jeng Ping

doi:10.1109/ted.2013.2263298

Cited by 45 publications

(13 citation statements)

References 17 publications

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“…The tantalum diffusion barrier layer is 20 nm thick, and can be neglected in the stress simulations [17]. The material physical properties used in the simulations (as shown in Table II) were set the same as those reported by Tsai et al [17]. For silicon, anisotropic modulus and Poisson's ratio were used.…”

Section: A Stress Modeling and Simulationsmentioning

confidence: 99%

Study of Near-Surface Stresses in Silicon Around Through-Silicon Vias at Elevated Temperatures by Raman Spectroscopy and Simulations

Zhu

Zhang²,

et al. 2015

IEEE Trans. Device Mater. Relib.

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The near-surface stress distribution around Cu through-silicon vias (TSVs) was studied by micro-Raman spectroscopy along with finite-element analysis from room temperature to 100 • C. Temperature-dependent measurements, along with simulations, revealed that the stresses near TSVs can have two components: 1) the preexisting stress before copper filling; and 2) the coefficients of thermal expansion (CTE)-mismatch-induced stress. The CTE-mismatch-induced stress resulted in a mobility change, and a keep-out zone (KOZ) at elevated temperatures was also estimated, where the KOZ was defined as the region with a mobility change larger than or equal to 10%. Higher temperatures were shown to reduce the CTE-mismatch-induced stress component and resulted in the shrinkage of KOZs in Si. The preexisting stress was shown to be significant in a region equal to or larger than the KOZs induced by the CTE-mismatch-induced stress only and should be characterized and considered in the KOZ determination and the circuit design. Index Terms-3-D integrated circuit (IC), keep-out zone (KOZ), mobility, stress, through silicon via (TSV).

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Section: A Stress Modeling and Simulationsmentioning

confidence: 99%

Study of Near-Surface Stresses in Silicon Around Through-Silicon Vias at Elevated Temperatures by Raman Spectroscopy and Simulations

Zhu

Zhang²,

et al. 2015

IEEE Trans. Device Mater. Relib.

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“…The nearest TSVs are standing 50 lm away from this point (see Fig. 5e), while negligible TSV-induced stress gradients are commonly found beyond a distance of 10 lm [4,22].…”

Section: Resultsmentioning

confidence: 96%

“…As a result of the confinement of metal filled TSVs and the coefficient of thermal expansion (CTE) mismatch with the surrounding Si matrix, stress is generated both in the TSV and in the surrounding Si. The local stresses induced by the CTE differences and by the process temperatures have proven to be detrimental in a thin-die integration flow in particular in terms of performances or even reliability as it can introduce Si cracking and performance degradation of devices [3,4]. It has been reported that a stress of 100 MPa can change carrier mobility in Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET) devices by more than 7% [5].…”

Section: Introductionmentioning

confidence: 99%

Strain and tilt mapping in silicon around copper filled TSVs using advanced X-ray nano-diffraction

Vianne

Escoubas

Richard

et al. 2015

Microelectronic Engineering

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“…The anisotropic property of silicon and elasto-plastic property of copper are taken into account, and silicon dioxide is treated to be liner elastic. The stiffness matrixes of silicon substrate for devices with [100] and [110] channel alignments are given as follows [9] C Si ½100 ¼ The plastic property parameters of copper are: 240 MPa@0ε, 250 MPa@0.008ε, and 260 MPa@0.01ε, where ε represents the thermal strain. Besides, the elastic property parameters of copper and silicon dioxide are: E Cu ¼ 110 GPa, and Cu ¼ 0:35 for copper, and E SiO2 ¼ 72 GPa, and SiO2 ¼ 0:16 for silicon dioxide, respectively.…”

Section: Koz Induced By Coaxial Tsvmentioning

confidence: 99%

Effects of coaxial through-silicon via on carrier mobility along [100] and [110] crystal directions of (100) silicon

Wang

Zhu

et al. 2015

IEICE Electron. Express

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This letter investigates the effects of coaxial through-silicon via (TSV) on carrier motilities in the channels of nMOS and pMOS with channels along [100] and [110] orientations on (100) silicon. The keep-out zone (KOZ) induced by coaxial TSV and the effective area occupied by TSV and surrounding KOZ are evaluated. The results show that, the effective area is reduced by ∼92% by aligning the channels of pMOS along [100] orientation and nMOS along [110] orientation than the opposite orientations. The absolute error ranges from −12.5 µm to 7.2 µm as the anisotropic property of silicon are neglected.

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Investigation on Cu TSV-Induced KOZ in Silicon Chips: Simulations and Experiments

Cited by 45 publications

References 17 publications

Study of Near-Surface Stresses in Silicon Around Through-Silicon Vias at Elevated Temperatures by Raman Spectroscopy and Simulations

Study of Near-Surface Stresses in Silicon Around Through-Silicon Vias at Elevated Temperatures by Raman Spectroscopy and Simulations

Strain and tilt mapping in silicon around copper filled TSVs using advanced X-ray nano-diffraction

Effects of coaxial through-silicon via on carrier mobility along [100] and [110] crystal directions of (100) silicon

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