(Invited) Boosting the On-Current of Si-Based Tunnel Field-Effect Transistors

Abstract

Tunnel-FETs (TFETs) have the potential for a sub-60 mV/dec subthreshold swing and therefore allow for scaling the supply voltage beyond the 1 V plateau of metal-oxide-semiconductor FETs (MOSFETs). The latter scaling is a necessary condition for a reduction of the power consumption per transistor. Silicon-based TFETs are the most attractive because they allow for a full re-use of the existing expertise in fabricating silicon MOSFETs. However, the large bandgap of silicon results in low on-currents. Therefore, the incorporation of heterostructures is proposed. In particular, a germanium-source silicon-channel n-TFET and, as complementary p-TFET, an indium(gallium)arsenide-source silicon-channel TFET reach on-currents comparable to MOSFETs. To beat the MOSFET performance and allow ultra-low voltage operation, additional performance boosters are required. We analyze the impact of the device configuration and of heterostructure strain. The former is illustrated with experimental data of all-silicon FinFET-based TFETs.

Dielectrically modulated hetero‐material double gate tunnel field‐effect transistor for label free biosensing

“…The advantage of using HfO 2 (a high-κ material) is that a low equivalent oxide thickness can be obtained without decreasing the physical thickness of the gate, thus avoiding the problem of direct tunneling of the carriers through the gate. [20][21][22][23][24] The length of the channel is 50 nm. The gates are made with metal of work function 4.64 eV.…”

“…The gate dielectric is made of two layers of silicon dioxide (SiO 2 ) and hafnium oxide (HfO 2 ) with thickness of 0.5 and 1.5 nm, respectively. The advantage of using HfO 2 (a high‐κ material) is that a low equivalent oxide thickness can be obtained without decreasing the physical thickness of the gate, thus avoiding the problem of direct tunneling of the carriers through the gate 20–24 . The length of the channel is 50 nm.…”

Trends and Challenges in Si and Hetero-Junction Tunnel Field Effect Transistors

“…Simulations have pointed that scaling the gate dielectric has a beneficial impact on the drive current, and is more important than scaling the film thickness [9,20]. The devices configuration, i.e., single, double or gate all around (GAA) has also an impact on the device performance.…”

Trends and Challenges in Si and Hetero-Junction Tunnel Field Effect Transistors

“…implantation profiles, anneal conditions (RTA, spike, laser, SPER etc), gate stack and spacer engineering, and design aspects [3,4]. In the presentation several critical issues will be demonstrated by TFET work on going at IMEC [2][3][4][5][6]. First some technological challenges for both vertical and horizontal devices are addressed.…”