(Invited) Comparative Simulation Study of InAs/Si and All-III-V Hetero Tunnel FETs

Schenk, Andreas; Sant, Saurabh; Moselund, Kirsten E.; Riel, Heike

doi:10.1149/06605.0157ecst

Cited by 9 publications

(3 citation statements)

References 27 publications

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“…The possibility of obtaining a negative transconductance regime in narrow nanowire TFETs was suggested in Refs. [18,19]. The transfer characteristics of the present TFET give an evidence of this phenomenon.…”

Section: Origin Of Negative Transconductance At High Gate Voltagessupporting

confidence: 66%

Impact of Non-idealities on the Performance of InAs/(In)GaAsSb/GaSb Tunnel FETs

Sant¹,

Memišević²,

Wernersson³

et al. 2018

CompoNano

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Measured InGaAsSb/InAs nanowire TFETs showing both, sub-60mV/dec slope and high ON-current, are simulated using calibrated TCAD. The focus is laid on the impact of non-idealities, such as hetero-interface traps, oxideinterface traps, and bulk traps on device characteristics. Simulated temperature-dependent transfer curves are in good agreement with the measured data which validates the simulation setup. It is found that trap-assisted tunneling involving bulk traps adjacent to the hetero-junction is primarily responsible for the degradation of the swing. Due to the small diameter of the nanowire, trap-assisted tunneling is inhibited at the InAs/oxide interface. Still, oxide interface traps reduce the electrostatic coupling between gate and channel, which further increases the swing. The TCAD analysis correctly predicts the negative transconductance observed at high gate bias. If the same simulation setup is used to study the effect of gate alignment, a significant improvement of both ON-current and swing is found.

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Section: Origin Of Negative Transconductance At High Gate Voltagessupporting

confidence: 66%

Impact of Non-idealities on the Performance of InAs/(In)GaAsSb/GaSb Tunnel FETs

Sant¹,

Memišević²,

Wernersson³

et al. 2018

CompoNano

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“…This results in the source energy bands moving down which decreases the tunnelling transmission probability ( I D saturation). Further increasing V G widens the source depletion region and closes the entire tunnelling path, causing the BTBT prohibition 21 , 31 and the valley I D at point (4).…”

Section: Resultsmentioning

confidence: 99%

Reconfigurable signal modulation in a ferroelectric tunnel field-effect transistor

2023

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Reconfigurable transistors are an emerging device technology adding new functionalities while lowering the circuit architecture complexity. However, most investigations focus on digital applications. Here, we demonstrate a single vertical nanowire ferroelectric tunnel field-effect transistor (ferro-TFET) that can modulate an input signal with diverse modes including signal transmission, phase shift, frequency doubling, and mixing with significant suppression of undesired harmonics for reconfigurable analogue applications. We realize this by a heterostructure design in which a gate/source overlapped channel enables nearly perfect parabolic transfer characteristics with robust negative transconductance. By using a ferroelectric gate oxide, our ferro-TFET is non-volatilely reconfigurable, enabling various modes of signal modulation. The ferro-TFET shows merits of reconfigurability, reduced footprint, and low supply voltage for signal modulation. This work provides the possibility for monolithic integration of both steep-slope TFETs and reconfigurable ferro-TFETs towards high-density, energy-efficient, and multifunctional digital/analogue hybrid circuits.

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“…Deep centers are well known as the origin of leakage currents in many types of devices, e.g., tunnel FETs. 64 In the pin-junction of the In 0:53 Ga 0:47 As Esaki diode, such levels can facilitate field-enhanced multi-phonon recombination, zero-phonon defect-assisted tunneling, and resonant tunneling. 65 Models of the first two mechanisms are available in S-Device.…”

Section: Resolving the Theory-experiments Discrepancy: Defect-assisted Tunneling (Dat)mentioning

confidence: 99%