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We present a process for fabricating a field-effect transistor based on vertically standing InAs nanowires and demonstrate initial device characteristics. The wires are grown by chemical beam epitaxy at lithographically defined locations. Wrap gates are formed around the base of the wires through a number of deposition and etch steps. The fabrication is based on standard III–V processing and includes no random elements or single nanowire manipulation.

An n-type InAs/InAsP heterostructure nanowire field-effect transistor has been fabricated and compared with a homogeneous InAs field-effect transistor. For the same device geometry, by introduction of the heterostructure, the threshold voltage is shifted 4 V, the maximum current on-off ratio is enhanced by a factor of 10,000, and the subthreshold swing is lowered by a factor 4 compared to the homogeneous transistor. At the same time, the drive current remains constant for a fixed gate overdrive. A single nanowire heterostructure transistor has a transconductance of 5 muA/V at a low source-drain voltage of 0.3 V. For the homogeneous InAs transistor, we deduced a high electron mobility of 1500 cm2/Vs.

Abstract-We present results on fabrication and dc characterization of vertical InAs nanowire wrap-gate field-effect transistor arrays with a gate length of 50 nm. The wrap gate is defined by evaporation of 50-nm Cr onto a 10-nm-thick HfO 2 gate dielectric, where the gate is also separated from the source contact with a 100-nm SiO x spacer layer. For a drain voltage of 0.5 V, we observe a normalized transconductance of 0.5 S/mm, a subthreshold slope around 90 mV/dec, and a threshold voltage just above 0 V. The highest observed normalized on current is 0.2 A/mm, with an off current of 0.2 mA/mm. These devices show a considerable improvement compared to previously reported vertical InAs devices with SiN x gate dielectrics.