We present a process for fabricating a field-effect transistor based on vertically standing InAs nanowires and demonstrate initial device characteristics. The wires are grown by chemical beam epitaxy at lithographically defined locations. Wrap gates are formed around the base of the wires through a number of deposition and etch steps. The fabrication is based on standard III–V processing and includes no random elements or single nanowire manipulation.

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A new processing scheme for the fabrication of sub-100-nm-gate-length vertical nanowire transistors has been developed. InAs transistors with an 11 Â 11 nanowire matrix and 80 nm gate length have been realized by this process. The gate length is directly controlled via the thickness of the evaporated gate metal and is thus easily scalable. The demonstrated devices operate in depletion mode, and they show a maximum drive current of about 1 mA and a maximum transconductance of 0.52 mS at V g ¼ À0:5 V and V d ¼ 1 V.

Nanowire transistors are currently being evaluated as an emerging device technology. While numerous investigations have studied the performance of lateral transistors based on single nanowires, there are only a few studies of the fabrication and performance of vertical transistors with wrap-gates, so called WIGFETs. Based on our previous study of 800 nm gate length transistors [1], we have now scaled the technology to sub 100 nm gate length and study the lateral scaling of the nanowires in the transistor structure. It is demonstrated that the scaling provides a mean to adjust the threshold voltage of the transistor.InAs (n-type, 2-5x1017 cm-3) nanowires grown by Chemical Beam Epitaxy have been used in this study, since the InAs provides good n-type transport properties, a low ohmic contact resistance, and a useful Fermi-level pinning. In the transistors, 1 lx1I matrices of 3-gm-long nanowires that were covered with 40 nm SiNX were used. A Ti/Au gate was then formed in a direct evaporation process [2] and patterned by optical lithography. Notably, in this process the gate length is directly controlled by the thickness of the deposited film. After planarization, Ti/Au drain contacts were formed. Nanowire matrices with two different diameters, 55 and 70 nm, were included on the same sample and they were simultaneously processed to get a direct comparison of performances.The transistors were evaluated using the substrate as a common source. Both types of transistors showed good transistor characteristics with drive currents reaching 1 mA. The 55 nm diameter transistor showed the lower output conductance, since the transistor with 70 nm diameter nanowires had a punch through at VSd>JV and Vg lV, related to insufficient potential control in the body of the wire. Notably, the drive current was not substantially reduced as the diameter was scaled. The transfer characteristics were evaluated at Vsd=0.5V for a number of transistors and a maximum hysteresis of AV=0.1 V was observed. The transistors showed peak transconductances of about 0.30 mS at Vg -0.8 V and Vsd=0.5 V with higher values at increased Vsd. To evaluate the threshold voltage, the current was plotted as a function of the gate bias, since in the cylindrical geometry used and considering the short gate length, a deviation from the conventional Sqrt(Id) vs Vg may be expected. The deduced values for the threshold voltages group for the two different diameters used with Vt=-1.6 V and Vt=-1.25 V for the 70 and 55 nm nanowire diameter, respectively. A minimum spread, AVt=0.2 V, was observed for the transistors with the larger diameter. Finally, we also studied the subthreshold characteristics at Vsd=0.5 V and observed subthreshold slopes of S=1.4 V/decade and S=1.0 V/decade for 70 and 55 nm nanowire diameter, respectively.Based on the data, we conclude that sub 100 gate length nanowire transistors with good transistor characteristics may be fabricated in the vertical geometry. It is also shown that lateral scaling of the nanowire diameter may be used to adjust the ...