Development of a Vertical Wrap-Gated InAs FET

Thelander, Claes; Rehnstedt, C.; Fröberg, Lars; Lind, Erik; Mårtensson, Thomas; Caroff, Philippe; Löwgren, Truls; Ohlsson, Björn; Samuelson, Lars; Wernersson, Lars‐Erik

doi:10.1109/ted.2008.2005151

Cited by 93 publications

(85 citation statements)

References 21 publications

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“…As compared to previously published data [2,9], we note a larger subthreshold slope in these devices, 120 mV/decade as compared to 80 mV/decade. This can mainly be attributed to insufficient scaling of the wire diameter for this gate length, but also a high D it .…”

Section: Resultssupporting

confidence: 64%

“…Other studies on advanced structures with comparable gate length, though including more measured devices, show up to five orders of magnitude in variation [7]. As a reference, we also measured the LFN for devices with varying number of nanowires (7)(8)(9)(10)(11)(12)(13)(14)(15)(16)(17)(18)(19), where we observed the CNSD level to decrease slightly as the number of wires was increased. In Figure 2b, CNSD for NW 1 and 2 is plotted versus the drain current at a constant frequency of 10 Hz.…”

Section: Resultsmentioning

confidence: 99%

“…The NW FETs are fabricated from epitaxially grown InAs nanowires with a diameter of 40 nm, grown on an <111>-B InAs substrate [2,9]. The wires are Sn-doped with a molar fraction of 3.49x10 -8 .…”

Section: Device Fabricationmentioning

confidence: 99%

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Low-Frequency Noise in Vertical InAs Nanowire FETs

Persson

Lind

Dey

et al. 2010

IEEE Electron Device Lett.

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Section: Resultssupporting

confidence: 64%

Section: Resultsmentioning

confidence: 99%

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Low-Frequency Noise in Vertical InAs Nanowire FETs

Persson

Lind

Dey

et al. 2010

IEEE Electron Device Lett.

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“…Epitaxially grown semiconductor nanowires (NWs) have generated much research interest lately because of their unique potential as building blocks of future electronic/photonic devices [1][2][3][4][5]. Because lattice strain allows elastic deformation without introducing misfit dislocations due to ultra-small growth regions [6], it is possible to achieve integration of III-V compound NWs on silicon platform [7].…”

Section: Introductionmentioning

confidence: 99%

Influence of growth temperature on growth of InGaAs nanowires in selective-area metal–organic vapor-phase epitaxy

Kohashi

Sato

Ikejiri

et al. 2012

Journal of Crystal Growth

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Indium-rich InGaAs nanowires were grown on an InP(111)B substrate by catalyst-free selective-area metal-organic vapor phase epitaxy, and its growth-temperature dependence of growth rate and composition was studied. In particular, nanowire growth rate rapidly decreases as growth temperature increases. This tendency is opposite (for a similar temperature range) to that found in a previous study on selective-area growth of gallium-rich InGaAs nanowires. This difference between indium-rich and gallium-rich nanowires suggests that the influence of growth temperature on the growth of InGaAs nanowires is dependent on the group-III supply ratio. On the basis of previous experimental observations in InAs and GaAs nanowires, temperature dependence of nanowire growth rate and its dependence on group-III supply ratio are predicted. A guideline to determine the optimum growth conditions of InGaAs nanowires is also discussed. Keywords:A1. Nanostructures

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“…15 The performance is also competitive with metal/oxide wrap-gated nanowire transistors, where subthreshold swings typically range from 100 to 750 mV/decade. 15,18,[36][37][38][39] This is particularly impressive as the polymer electrolyte does not completely wrap around the nanowire in our devices, unlike in Ref. 11 where a HF etch was used to 'undercut' the nanowire to provide access for the PEO/LiClO 4 film.…”

mentioning

confidence: 96%

Electron-Beam Patterning of Polymer Electrolyte Films To Make Multiple Nanoscale Gates for Nanowire Transistors

et al. 2013

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We report an electron-beam based method for the nanoscale patterning of the poly(ethylene oxide)/LiClO 4 polymer electrolyte. We use the patterned polymer electrolyte as a high capacitance gate dielectric in single nanowire transistors and obtain subthreshold swings comparable to conventional metal/oxide wrap-gated nanowire transistors. Patterning eliminates gate/contact overlap which reduces parasitic effects and enables multiple, independently controllable gates. The method's simplicity broadens the scope for using polymer electrolyte gating in studies of nanowires and other nanoscale devices.

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Development of a Vertical Wrap-Gated InAs FET

Cited by 93 publications

References 21 publications

Low-Frequency Noise in Vertical InAs Nanowire FETs

Low-Frequency Noise in Vertical InAs Nanowire FETs

Influence of growth temperature on growth of InGaAs nanowires in selective-area metal–organic vapor-phase epitaxy

Electron-Beam Patterning of Polymer Electrolyte Films To Make Multiple Nanoscale Gates for Nanowire Transistors

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