Vertical high-mobility wrap-gated InAs nanowire transistor

Bryllert, Tomas; Wernersson, Lars‐Erik; Fröberg, Lars; Samuelson, Lars

doi:10.1109/led.2006.873371

Cited by 345 publications

(241 citation statements)

References 10 publications

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“…Studies have also demonstrated the high electron mobil ity of epitaxial InAs NWFETs with a wrap -around cylindrical gate structure surrounding a nanowire. 48 More generally, controlled bottom -up assembly and synthetic elaboration of NWs offers unique opportunities. The crossed NW architecture enables device properties to be defined by the assembly of the NW components and not by lithography, and has been utilized to demonstrate logic gate structures, basic computation, and selective addressing.…”

Section: Nanoelectronic Devicesmentioning

confidence: 99%

Functional Nanowires

Lieber¹,

Wang²

2007

MRS Bull.

981

761

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Nanotechnology offers the promise of enabling revolutionary advances in diverse areas ranging from electronics, optoelectronics, and energy to healthcare. Underpinning the realization of such advances are the nanoscale ma te rials and corresponding nanodevices central to these application areas. Semiconductor nanowires and nanobelts are emerging as one of the most powerful and diverse classes of functional nanoma terials that are having an impact on science and technology. In this issue of MRS Bulletin, several leaders in this vibrant field of research present brief reviews that highlight key aspects of the underlying ma te rials science of nanowires, basic device functions achievable with these ma te rials, and developing applications in electronics and at the interface with biology. This ar ticle introduces the controlled synthesis, patterned and designed self -assembly, and unique applications of nanowires in nanoelectronics, nano -optoelectronics, nanosensors, nanobiotechnology, and energy harvesting.

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Section: Nanoelectronic Devicesmentioning

confidence: 99%

Functional Nanowires

Lieber¹,

Wang²

2007

MRS Bull.

981

761

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“…The obtained mobility for three different temperatures are shown in Fig. 4(a) as a function of the Fermi level g. The value of around 2000 cm 2 /Vs at room temperature is greater than the field effect mobilities of Ghoneim et al 10 and Lin et al 11 but smaller than the value of Bryllert et al 12 and Dayeh et al 13 The solid lines in Fig. 4(a) are computed using s o as fitting parameter.…”

mentioning

confidence: 90%

Using the Seebeck coefficient to determine charge carrier concentration, mobility, and relaxation time in InAs nanowires

Schmidt

Mensch

Karg

et al. 2014

Applied Physics Letters

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A method for determining charge carrier concentration, mobility, and relaxation time in semiconducting nanowires is presented. The method is based on measuring both the electrical conductivity and the Seebeck coefficient of the nanowire. With knowledge on the bandstructure of the material, Fermi level and charge carrier concentration can be deduced from the Seebeck coefficient. The ratio of measured conductivity and inferred charge carrier concentration then leads to the mobility, and using the Fermi level dependence of mobility one can finally obtain the relaxation time. Using this approach we exemplarily analyze the characteristics of an n-type InAs nanowire.

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“…5 The well-known problem here is that free surfaces and MIS interfaces of III-V semiconductors generally possess high density of surface/ interface states which pin the Fermi level and cause various unwanted problems. In nanoscale devices controlled by nanoscale electrodes, the surface-to-volume ratio is increased, and such problems become more serious.…”

Section: Introductionmentioning

confidence: 99%

Formation of ultrathin SiNx∕Si interface control double layer on (001) and (111) GaAs surfaces for ex situ deposition of high-k dielectrics

Akazawa

Hasegawa

2007

Journal of Vacuum Science &Amp; Technology B: Microelectronics and Nanometer Structures Processing, Measurement, and Phenomena

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In order to realize pinning-free high-k dielectric metal-insulator-semiconductor ͑MIS͒ gate stack on ͑001͒ and ͑111͒B oriented GaAs surfaces using the Si interface control layer ͑Si ICL͒ concept, formation of a SiN x / Si ICL double layer was investigated as a chemically stable structure on ͑001͒ and ͑111͒B surfaces which allows ex situ deposition of HfO 2 high-k dielectric films without losing the benefit of Si ICL. First, Si ICLs grown by molecular beam epitaxy ͑MBE͒ on ͑001͒ and ͑111͒B GaAs surfaces with various initial surface reconstructions were investigated in detail by reflection high energy electron diffraction and x-ray photoelectron spectroscopy ͑XPS͒ investigations at each step of the interface formation. Large shifts of the surface Fermi level position toward unpinning were observed after Si ICL growth on appropriately formed Ga-stabilized surfaces. It was found that Si layers grow epitaxially with Si-Ga bonds at the Si/ GaAs interface and Si-As termination on top, suggesting surfactant roles played by As atoms. Then, an ultrathin SiN x buffer film was formed on the Si ICL by its in situ partial nitridation in the MBE chamber. An XPS analysis of the resultant SiN x / Si ICL double layer formed on ͑001͒ and ͑111͒B surface indicated that the structure is chemically stable against air exposure on both surfaces in the sense that it prevents the host GaAs surface from subcutaneous oxidation, although SiN x film itself partially turns into SiO x N y . Finally, high-k MIS capacitors were formed by ex situ deposition of HfO 2 on the SiN x / Si ICL/GaAs structure after transferring the sample through air. The capacitance-voltage ͑C-V͒ analysis indicated that the MIS interface is completely pinning-free with a minimum interface state density in the range of low 10 11 cm −2 eV −1 .

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Vertical high-mobility wrap-gated InAs nanowire transistor

Cited by 345 publications

References 10 publications

Functional Nanowires

Functional Nanowires

Using the Seebeck coefficient to determine charge carrier concentration, mobility, and relaxation time in InAs nanowires

Formation of ultrathin SiNx∕Si interface control double layer on (001) and (111) GaAs surfaces for ex situ deposition of high-k dielectrics

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