(Invited) FinFET Flash Memory Technology

Abstract

The crystal-Si and poly-Si fin-channel flash memories with a thin n+-poly-Si floating-gate (FG) layer have successfully been fabricated, and their electrical characteristics have systematically been investigated. It was experimentally found that the better short-channel effect (SCE) immunity, the smaller threshold voltage (Vt) variations and a higher program speed are obtained in the crystal-Si fin-channel tri-gate (TG)-type flash memories than in the double-gate (DG)-type ones. It was also confirmed that split-gate crystal-Si fin-channel flash memories show highly suppressed over-erase as compared to that in stack-gate memories. Moreover, it was found that Vt variation in the poly-Si fin-channel flash memories after a program/erase (P/E) cycle became comparable to that in the crystal-Si fin-channel memories. The measured source-drain breakdown voltage (BVDS) was higher than 3.2 V even the gate length (Lg) was down to 76 nm. The developed technology is very useful for the fabrication of scaled NOR-type flash memory.

Experimental study of three-dimensional fin-channel charge trapping flash memories with titanium nitride and polycrystalline silicon gates

“…Data retention of the fabricated SONOS-and MONOS-type flash memories was also evaluated at room 100 k cycles temperature, as shown in Figs. 16(a) and 16(b). Note that these two types of flash memory can maintain reasonable memory windows after 10 years.…”

“…The slope of the Pelgrom plot, i.e., A Vt , is about 5.4 mV µm, which is much larger than that of conventional FinFETs because of the large equivalent gate oxide thickness of ONO layers. 16,17) To suppress SCE effectively at L g smaller than 46 nm, further miniaturization of 3D fin channels is indispensable, the process for which is under development.…”

“…[1][2][3][4][5][6][7][8][9][10][11][12] Moreover, the threshold voltage (V t ) variability in FinFETs is much smaller than that in conventional bulk planar metal-oxide-semiconductor field-effect transistors (MOSFETs) because the randomdopant-fluctuation (RDF)-induced variation in V t is negligible in FinFETs owing to undoped fin channels. [13][14][15][16][17][18][19] Therefore, scaled fin-channel flash memory cell transistors using siliconon-insulator (SOI)-based and body-tied bulk silicon (Si) fin channels have been actively developed, and the scalability of fin-channel flash memories down to a gate length (L g ) of 20 nm has been demonstrated. [20][21][22][23][24][25][26][27][28][29] However, the gate material dependence of the electrical characteristics of SOIbased FinFET flash memories has not been investigated sufficiently.…”

Investigation of piezoresistive effect in p-channel metal–oxide–semiconductor field-effect transistors fabricated on circular silicon-on-insulator diaphragms using cost-effective minimal-fab process

“…After the formation of the SD doping areas, a 6-nm-thick gate oxide layer (T ox ) was formed by thermal oxidation at 900 °C for 10 min, and a 30-nm-thick physical-vapor-deposited (PVD) titanium nitride (TiN) layer was deposited as a gate material. [22][23][24][25][26][27][28] Since PVD-TiN has a midgap work function, a negative threshold voltage (V t ) can be obtained for PMOSFETs. After the deposition of a 54-nm-thick TEOS-SiO 2 layer, gate electrodes were also fabricated using the minimal-fab maskless exposure machine and wet etching process, followed by the deposition of a 134-nm-thick TEOS-SiO 2 layer and the formation of contact holes, as shown in Fig.…”

Memristive operation mode of floating gate transistors: A two-terminal MemFlash-cell

“…Moreover, because the MemFlash-cell is based simply on a modified wiring scheme, all current approaches such as charge trapping (e.g., silicon-oxide-nitride-oxide-silicon (SONOS)), nanocrystal floating gates, three-dimensional circuits, a sub-threshold operation or FinFETs designs can be implemented. 24,[31][32][33][34] Nonetheless, despite the problem of power consumption, MemFlash-cells could be used to demonstrate the proof of principles of two terminal devices in circuit architectures. Especially, for this purpose and in comparison to state-ofthe-art memristive devices, a Si-based fabrication technology, including small parameter spreads and a high yield, offers an interesting alternative for currently available memristive devices based on partly ionic mechanisms.…”