2014
DOI: 10.1149/06405.0253ecst
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(Invited) Wafer-Level Integration of Embedded Cooling Approaches

Abstract: New thermal management solutions to keep components within thermal limits are needed to fully exploit the potential of 3D integration of ICs yielding dense electronic systems with increased performance and power efficiency. A roadmap from embedded single-side towards 3D interlayer cooling is presented. The characteristics of single-phase water and two-phase dielectric cooling are discussed further. Dual-side cooling was identified as an intermediate step considering an active cooled interposer combining therma… Show more

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Cited by 3 publications
(1 citation statement)
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“…The main goal here is to approximately simulate a thermal sink region for a chip stack on a "system on Package" (SoP) electronics package [21] and prepare in-situ a G 0 thermally conductive film to dissipate the heat produced by the tightly packed transistors in SoP (details in the Experimental Methods).…”
Section: S25 Preparation Of Films On Complex Surfaces and Confined Sp...mentioning
confidence: 99%
“…The main goal here is to approximately simulate a thermal sink region for a chip stack on a "system on Package" (SoP) electronics package [21] and prepare in-situ a G 0 thermally conductive film to dissipate the heat produced by the tightly packed transistors in SoP (details in the Experimental Methods).…”
Section: S25 Preparation Of Films On Complex Surfaces and Confined Sp...mentioning
confidence: 99%