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Two-phase liquid cooling of computer chips via microchannels etched directly on silicon dies is a potential long-term solution to enable continued integration of high-performance multiprocessors. Two-phase cooling refers to the heat removal via evaporation of a refrigerant flowing inside a heat sink. While possessing superior cooling properties, largescale use of this technology in the industry is limited by the lack of thermal modeling tools that can accurately predict temperatures in a two-phase cooled IC. In this paper, we propose STEAM, a new compact thermal model for 2D/3D ICs with two-phase cooling via silicon microchannels. The accuracy of the STEAM model is validated against measurements from a real two-phase cooled IC test stack reported previously in literature. Temperatures were predicted with an average error as low as 10.2% for uniform heat fluxes and 6.9% for hotspots. Finally, the STEAM model is applied to a realistic 3D multiprocessor system-on-chip (3D MPSoC) with two-phase cooling to simulate IC temperatures and the refrigerant pumping power, demonstrating the applicability of STEAM in the early-stage design of near-future high-performance computers with two-phase cooling.

Abstract-Three-dimensional (3D) stacking of integratedcircuit (IC) dies by vertical integration increases system density and package functionality. The vertical integration of IC dies by area-array Through-Silicon-Vias (TSVs) reduces the length of global interconnects and accordingly the signal delay time. On the other hand, the ongoing miniaturization trend of ICs results in constantly increasing chip-level power densities. Thus, the development of new chip cooling concepts is of utmost importance. Therefore, scalable cooling solutions for chip stacks, such as interlayer cooling, need to be investigated. This paper presents a new concept for the integration of intra chip stack fluidic cooling, namely die-embedded microchannels for single-and twophase thermal management, using a patterned thin-layer eutectic solder bonding technique for the stack assembly. Results showed the successful fabrication of 5-layer chip stacks with embedded microchannels and high aspect ratio TSVs. Optical inspections demonstrated the proper bond line formation and direct current (DC) daisy-chain electrical tests indicated the successful combination of TSVs with thin-layer solder interconnects. Mechanical shear tests on die-on-die bonded samples showed the strength of the patterned thin-layer solder bond (16MPa). An added solder ring-pad component to seal the electrically active pad from any conductive liquid coolant was also investigated and reflow tests on such geometries showed the appearance of a balling effect along the solder ring line. This balling was found to be mitigated when the ring aspect ratio (deposited solder height to ring width ratio) was kept below the experimentally observed critical value of 0.65.

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