Integration of intra chip stack fluidic cooling using thin-layer solder bonding

Abstract

Abstract-Three-dimensional (3D) stacking of integratedcircuit (IC) dies by vertical integration increases system density and package functionality. The vertical integration of IC dies by area-array Through-Silicon-Vias (TSVs) reduces the length of global interconnects and accordingly the signal delay time. On the other hand, the ongoing miniaturization trend of ICs results in constantly increasing chip-level power densities. Thus, the development of new chip cooling concepts is of utmost importance. Therefore, scalable cooling solutions for chip stacks, such as interlayer cooling, need to be investigated. This paper presents a new concept for the integration of intra chip stack fluidic cooling, namely die-embedded microchannels for single-and twophase thermal management, using a patterned thin-layer eutectic solder bonding technique for the stack assembly. Results showed the successful fabrication of 5-layer chip stacks with embedded microchannels and high aspect ratio TSVs. Optical inspections demonstrated the proper bond line formation and direct current (DC) daisy-chain electrical tests indicated the successful combination of TSVs with thin-layer solder interconnects. Mechanical shear tests on die-on-die bonded samples showed the strength of the patterned thin-layer solder bond (16MPa). An added solder ring-pad component to seal the electrically active pad from any conductive liquid coolant was also investigated and reflow tests on such geometries showed the appearance of a balling effect along the solder ring line. This balling was found to be mitigated when the ring aspect ratio (deposited solder height to ring width ratio) was kept below the experimentally observed critical value of 0.65.

Characterization of TSV etch from a sustainability standpoint

“…All DRIE processing was carried out in an inductively-coupled plasma (ICP) etch chamber and the baseline process-a modified Bosch etch-has been previously described. 15 As shown in Figure 1 (a), step 1: an etching gas (SF6) is flowed with no power allowing for chamber stabilization for the etch step, step 2: source power (continuous wave, CW) and bias power (pulsed) are applied and the etch process proceeds, step 3: source power, bias power and SF6 gas flow are turned off and passivating gas (C4F8) is flowed allowing for chamber stabilization for the passivation step, step 4: source power (CW) and bias power (pulsed) are turned on and the passivation process proceeds. Bias pulsing (where used) was fixed at a frequency of 500Hz and a duty cycle of 50%.…”

High-aspect ratio through-silicon vias for the integration of microfluidic cooling with 3D microsystems

“…Thus, small TSV dimensions are preferable since they not only minimize the silicon real-estate footprint, but they also improve the electrical performances. While prior work has shown the integration of TSVs in a microfluidic heat sink [9,11], the reported TSVs were very large in diameter (50-60 μm) and with an aspect ratio of only 5:1, leading to large electrical parasitics. Prior work [10] shows preliminary effort in the fabrication of 18:1 aspect ratio TSVs within a microfluidic heat sink.…”

“…Typically, to achieve higher cooling capability, a microfluidic heat sink requires each chip to be relatively thick, since the height of the heat sink is strongly related to its cooling capability. In prior work, the thickness of dice with an embedded microfluidic heat sink was shown to be a few hundred micrometers [6][7][8][9][10][11]. While such thickness is attractive from a thermal point of view, this inevitably increases TSV dimensions (diameter and height) and thus, TSV capacitance, which impacts latency and energy dissipation.…”

Evaluation of the Potential Electromagnetic Interference in Vertically Stacked 3D Integrated Circuits

“…ICs are often the primary source of radiated emissions, and near field magnetic field can help engineers to track down EMI culprit and solve the . Three-dimensional stack-dies integrated circuits (3D-ICs) trend for vertical distance between ICs [16][17][18][19][20][21][22][23].…”