InvMixColumn decomposition and multilevel resource sharing in AES implementations

Fischer, Viktor; Drutarovský, Miloš; Chodowiec, Paweł; Gramain, F.

doi:10.1109/tvlsi.2005.853606

Cited by 31 publications

(20 citation statements)

References 2 publications

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“…The efficient implementation of the AES algorithm on FPGA is being under discussion from last several years in terms of throughput, minimum area requirement, and high speed [11][12][13][14][15][16]. The main reason to choose FPGA for the implementation of cryptographic algorithms is that it allows changing design with no additional time cost while the design cycle is also very short.…”

Section: Fpga Implementation Of Aes Pipelined Architecturementioning

confidence: 99%

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FPGA implementation of AES-based crypto processor

Anwar

Daneshtalab

Ebrahimi

et al. 2013

2013 IEEE 20th International Conference on Electronics, Circuits, and Systems (ICECS)

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Increased demand for data security is an undeniable fact. Towards achieving higher security, cryptographic algorithms play an important role in the protection of data from unapproved usage. In this paper, we present a crypto processor using Advanced Encryption Standard (AES). The AES is integrated with a 32-bit general purpose 5-stage pipelined MIPS processor. The integrated AES module is a fully pipelined module which follows inner round and outer round pipeline design. The results show that the presented pipeline version of the AES algorithm along with MIPS processor outperforms traditional methods. At the operating frequency of 553 MHz, the proposed design can achieve the throughput of 58 Gbps, the latency of 240 ns, and the minimum power consumption of 76 mw.

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Section: Fpga Implementation Of Aes Pipelined Architecturementioning

confidence: 99%

“…The main reason to choose FPGA for the implementation of cryptographic algorithms is that it allows changing design with no additional time cost while the design cycle is also very short. An FPGA based AES implementation is presented in [3][4][5][6][7][8][9][10][11][12][13][14]. Fig.…”

Section: Fpga Implementation Of Aes Pipelined Architecturementioning

confidence: 99%

FPGA implementation of AES-based crypto processor

Anwar

Daneshtalab

Ebrahimi

et al. 2013

2013 IEEE 20th International Conference on Electronics, Circuits, and Systems (ICECS)

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“…% Area (Shared/Non-shared) Lin et al [5] 85.8% LUTs Fischer et al [6] 52.6 -77.7% Mondal and Memik [8] 50.8 -91.1 Memik et al [7] 56% Proposed approach 47.5 -93.1%…”

Section: Approachesmentioning

confidence: 99%

Configuration Sharing to Reduce Reconfiguration Overhead Using Static Partial Reconfiguration

Jung

Kim

2008

IEICE Transactions on Information and Systems

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SUMMARY Reconfigurable architectures are one of the most promising solutions satisfying both performance and flexibility. However, reconfiguration overhead in those architectures makes them inappropriate for repetitive reconfigurations. In this paper, we introduce a configuration sharing technique to reduce reconfiguration overhead between similar applications using static partial reconfiguration. Compared to the traditional resource sharing that configures multiple temporal partitions simultaneously and employs a time-multiplexing technique, the proposed configuration sharing reconfigures a device incrementally as an application changes and requires a backend adaptation to reuse configurations between applications. Adopting a data-flow intermediate representation, our compiler framework extends a min-cut placer and a negotiation-based router to deal with the configuration sharing. The results report that the framework could reduce 20% of configuration time at the expense of 1.9% of computation time on average.

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“…Most of the existing implementations of AES address MC and IMC separately, except some recent implementations which have demonstrated potential for resource sharing between MC and IMC leading to speed and area optimizations [5], [14], [2], [4], [7], [8], [9], [10]. Combined MC/IMC design suggested in [9] was based on serial/parallel decomposition of the matrix and then minimising the logic using common subexpressions elimination method.…”

Section: Introductionmentioning

confidence: 99%

“…Combined MC/IMC design suggested in [9] was based on serial/parallel decomposition of the matrix and then minimising the logic using common subexpressions elimination method. Decomposition of MC with respect to FPGA structure suggested by Ghaznavi et.…”

Section: Introductionmentioning

confidence: 99%

Mix/InvMixColumn decomposition and resource sharing in AES

Iyer

Deepa

Anandmohan

et al. 2010

2010 5th International Conference on Industrial and Information Systems

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In this paper, compact architectures for AES Mix Column and its inverse is presented to reduce the area cost in resulting AES implementation. In the hardware implementation of AES with direct mapping substitute byte optimization, MixColumn/Inverse MixColumn transformation demands the utilization of logic resources and then effects the critical path delay and resulting throughput. The proposed MixColumn/Inverse MixColumn design based on byte and bit-level decomposition leads to two types of architecture which demonstrates deeper resource sharing within byte and between bytes and rearrangement of output terms with respect to FPGA architecture in bit level resply.The proposed architectures have been investigated on a FPGA based implementation platform. Application of the proposed architectures resulted in reduction of reconfigurable logic area by 40% as compared to separate implementation of MixColumn and Inverse MixColumn reduction and also path delay by 9% resply. Experimental results show that our proposed architecture can reduce the area cost significantly and compared with other previous implementations reported so far.

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InvMixColumn decomposition and multilevel resource sharing in AES implementations

Cited by 31 publications

References 2 publications

FPGA implementation of AES-based crypto processor

FPGA implementation of AES-based crypto processor

Configuration Sharing to Reduce Reconfiguration Overhead Using Static Partial Reconfiguration

Mix/InvMixColumn decomposition and resource sharing in AES

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