Ion-Beam-Induced Defects in CMOS Technology: Methods of Study

Fedorenko, Yanina

doi:10.5772/67760

Cited by 5 publications

(4 citation statements)

References 142 publications

(184 reference statements)

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“…The first step of the STT-MRAM manufacturing process is the FEOL process where transistors are fabricated on the wafer. In this phase, typical defects may occur such as semiconductor impurities, crystal imperfections, pinholes in gate oxides, and shifting of dopants [31]. These are the conventional defects which have been sufficiently studied and are generally modeled by resistive opens, shorts and bridges [32][33][34].…”

Section: Feol Defectsmentioning

confidence: 99%

Defect and Fault Modeling Framework for STT-MRAM Testing

Rao

Taouil

et al. 2021

IEEE Trans. Emerg. Topics Comput.

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STT-MRAM mass production is around the corner as major foundries worldwide invest heavily on its commercialization. To ensure high-quality STT-MRAM products, effective yet cost-efficient test solutions are of great importance. This paper presents a systematic device-aware defect and fault modeling framework for STT-MRAM to derive accurate fault models which reflect the physical defects appropriately, and thereafter optimal and high-quality test solutions. An overview and classification of manufacturing defects in STT-MRAMs are provided with an emphasis on those related to the fabrication of magnetic tunnel junction (MTJ) devices, i.e., the data-storing elements. Defects in MTJ devices need to be modeled by adjusting the affected technology parameters and subsequent electrical parameters to fully capture the defect impact on both the device's electrical and magnetic properties, whereas defects in interconnects can be modeled as linear resistors. In addition, a complete single-cell fault space and nomenclature are defined, and a systematic fault analysis methodology is proposed. To demonstrate the use of the proposed framework, resistive defects in interconnect and pinhole defects in MTJ devices are analyzed for a single 1T-1MTJ memory cell. Test solutions for detecting these defects are also discussed.

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Section: Feol Defectsmentioning

confidence: 99%

Defect and Fault Modeling Framework for STT-MRAM Testing

Rao

Taouil

et al. 2021

IEEE Trans. Emerg. Topics Comput.

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show abstract

“…The first step of the STT-MRAM manufacturing process is the FEOL process where transistors are fabricated on the wafer. In this phase, typical defects may occur such as semiconductor impurities, crystal imperfections, pinholes in gate oxides, and shifting of dopants [111]. These are the conventional defects which have been sufficiently studied and are generally modeled by resistive opens, shorts and bridges [112][113][114].…”

Section: Conventional Defects In Feolmentioning

confidence: 99%

Testing STT-MRAM: Manufacturing Defects, Fault Models, and Test Solutions

Rao

Taouil

et al. 2021

2021 IEEE International Test Conference (ITC)

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“…This technique has been widely employed in the development of semiconductor devices and structures [16][17][18][19]. However, ion implantation can introduce complex defects that significantly impact the electrical and optical properties of the targeted device, because they can act as recombination centers, leading to substantial changes in the charge carrier profiles of the material [20][21][22]. Understanding the complex nature of intrinsic and impurity-related defects is crucial for comprehending and reconciling the electrical behavior of ZnO-based devices.…”

Section: Introductionmentioning

confidence: 99%

Fabrication and Analysis of Ion-Engineered ZnO Device Structures for Optoelectronic Applications

Younus,

Shuja,

Ali

2023

IEEE Photonics J.

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Abstract-ZnO-based devices are highly promising for applications involving light-matter interaction. This work explores the impact of light-matter interaction on ion-induced ZnO structures and their respective energy band profiles. Incorporation of various ions, (Au + , B + , Cu + , P + ) into the ZnO lattice, deposited via magnetron sputtering on an n-type Si substrate was investigated in detail. To assess the impact of these ions on the ZnO surface, monte-carlo simulations at low energies were performed and optimal ion dose and energy conditions were determined. The resulting post-fabrication devices underwent comprehensive structural, morphological, optical, and electrical diagnostics. X-ray diffraction (XRD) analysis confirmed the wellmaintained crystal structure of the ZnO lattice along the <100> direction for all implant sequences. Notably, the gold (Au + ) implant exhibited the highest light extinction into the ZnO matrix, as indicated by the extinction coefficient and refractive index data. This observation suggested that Au + implantation could effectively generate electron-hole pairs. The photovoltage and dark/light current measurements provided further evidence of enhanced light-matter interactions and responsivity in the Au + -implanted devices owing to light-induced currents. Furthermore, the energy bands of all implant cases were profiled by Charge Deep Level Transient Spectroscopy (Q-DLTS) measurements by evaluating discrete energy states within the ZnO lattice.

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Ion-Beam-Induced Defects in CMOS Technology: Methods of Study

Cited by 5 publications

References 142 publications

Defect and Fault Modeling Framework for STT-MRAM Testing

Defect and Fault Modeling Framework for STT-MRAM Testing

Testing STT-MRAM: Manufacturing Defects, Fault Models, and Test Solutions

Fabrication and Analysis of Ion-Engineered ZnO Device Structures for Optoelectronic Applications

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