Ising Model Optimization Problems on a FPGA Accelerated Restricted Boltzmann Machine

Abstract

Optimization problems, particularly NP-Hard Combinatorial Optimization problems, are some of the hardest computing problems with no known polynomial time algorithm existing. Recently there has been interest in using dedicated hardware to accelerate the solution to these problems, with physical annealers and quantum adiabatic computers being some of the state of the art. In this work we demonstrate usage of the Restricted Boltzmann Machine (RBM) as a stochastic neural network capable of solving these problems efficiently. We show that by mapping the RBM onto a reconfigurable Field Programmable Gate Array (FPGA), we can effectively hardware accelerate the RBM's stochastic sampling algorithm. We benchmark the RBM against the DWave 2000Q Quantum Adiabatic Computer and the Optical Coherent Ising Machine on two such optimization problems: the MAX-CUT problem and finding the ground state of a Sherrington-Kirkpatrick (SK) spin glass. On these problems, the hardware accelerated RBM shows best in class performance compared to these other accelerators, with an empirical scaling performance of O(e −N ) for probability of reaching the ground state compared to a similar empirical O(e −N ) for the CIM (with the RBM showing a constant factor of improvement over the CIM) and empirical O(e −N 2) for the DWave Annealer. The results show up to 10 7 x and 10 5 x time to solution improvement compared to the DWave 2000Q on the MAX-CUT and SK problems respectively, along with a 150x and 1000x performance increase compared to the Coherent Ising Machine annealer on those problems. By using commodity hardware running at room temperature for acceleration, the RBM also has greater potential for immediate and scalable use.

Quadratic Unconstrained Binary Optimisation via Quantum-Inspired Annealing

“…In its most basic form, our method uses a simple gradient descent update, which results in a different (un-physical) trajectory of the parameters θ. Under the momentum-assisted update (15) and in the continuous-time limit (i.e. for infinitesimal step size), it is known that a physical interpretation of our approach is possible [39]: namely, as a dynamical evolution of a system in a viscous medium in which the momentum parameter plays the role of mass.…”

“…At the same time, the interest in QUBO problems has inspired new classical algorithms [12][13][14][15][16][17] and corresponding optimization devices [18][19][20][21][22][23]. Since these algorithms can be run on digital logic, they can often handle orders of magnitude more variables than current quantum computers, and as such will serve as valuable classical benchmarks as quantum computers increase in size.…”

Probabilistic computing with p-bits

“…The p-computer can then provide N p f c samples per second, N p being the number of parallel units 8 , and f c the clock frequency. We argue that even with N p = 1, this throughput is well in excess of what is achieved with standard implementations on either CPU or GPU for a broad range of applications and algorithms including but not limited to those targeted by modern digital annealers or Ising solvers [9][10][11][12][13][14][15][16][17] . Interestingly, a p-computer also provides a conceptual bridge to quantum computing, sharing many characteristics that we associate with the latter.…”

“…In principle, the energy function is arbitrary, but much of the work is based on quadratic energy functions defined by a connection matrix W ij and a bias vector h i (see for example [9][10][11][12][13][14][15][16][17] ):…”

Quantitative Evaluation of Hardware Binary Stochastic Neurons

“…Given the importance of optimization problems, a lot of research has gone into developing algorithms and identifying appropriate hardware for Ising computing. Various approaches including quantum computers based on quantum annealing (QA) or adiabatic quantum optimization (AQC) implemented with superconducting circuits 11 , coherent Ising machines (CIMs) implemented with laser pulses 12 , phasechange oscillators 13 , or CMOS oscillators [14][15][16][17] and digital annealers based on simulated annealing (SA) 18 implemented with digital circuits 1,[19][20][21][22][23][24] are being explored.…”