Issues and Key Technologies for Next Generation 3D NAND

Yoon, Chi-Weon; Kim, Hyung-Gon; Lee, Seon-Kyoo; Lee, Jin-Yub; Song, Jay Hyok

doi:10.1109/iceic51217.2021.9369795

Cited by 5 publications

(3 citation statements)

References 11 publications

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“…While the increase of vertical stacks for further 3-D NAND technology, the difference of aspect ratio becomes a major issue in etching the channel hole [33]. Thus the gate length and intercell length should be shrink, which affects trapped charge distribution.…”

Section: Figure 6 (A) 2-d Conduction Energy Band Diagram (Ec) Along the Channel Direction (A-a') And (B) The Vertical Direction (B-b')mentioning

confidence: 99%

Extraction of Nitride Trap Profile in 3-D NAND Flash Memory Using Intercell Program Pattern

Park

Yoon

et al. 2021

IEEE Access

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The extraction of nitride trap density (Nt) filled with electrons emitted by thermal emission (TE) in the charge-trapping layer of 3-D NAND flash memory is demonstrated. The intercell program (IP) pattern was adopted to intentionally inject electrons into the intercell region to minimize the influence of lateral migration (LM) on the trap profiles. This was confirmed by the retention characteristics observed at 120 °C, where the charge loss is mainly caused by the TE of the trapped electrons in the nitride layer. The extracted peak value of Nt at EC-ET value of 1.20 eV using the IP pattern was as low as 1.01×10 19 cm -3 eV -1 , in the scan range of 0.96 eV to 1.27 eV. This value was 17% lower than that from the conventional adjacent cell program (P-P-P) pattern. Therefore, the IP pattern can be used in extracting trap profiles in the SiN layer in scaled 3-D NAND memories. INDEX TERMS 3D NAND flash memory, data retention, lateral migration, trap profilingThis work is licensed under a Creative Commons Attribution-NonCommercial-NoDerivatives 4.

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Section: Figure 6 (A) 2-d Conduction Energy Band Diagram (Ec) Along the Channel Direction (A-a') And (B) The Vertical Direction (B-b')mentioning

confidence: 99%

Extraction of Nitride Trap Profile in 3-D NAND Flash Memory Using Intercell Program Pattern

Park

Yoon

et al. 2021

IEEE Access

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“…Three-dimensional (3D) stackable NAND flash memory was invented to uphold the trends of increasing bit density and decreasing bit cost for each generation of NAND flash product [1][2][3]. To further achieve a minimal cell footprint and die size, the 3D NAND architecture with CMOS under an array replaced the CMOS below the NAND array.…”

Section: Introductionmentioning

confidence: 99%

A Novel Channel Preparation Scheme to Optimize Program Disturbance in Three-Dimensional NAND Flash Memory

You,

Jin,

Jia

et al. 2024

Micromachines

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The program disturbance characteristics of three-dimensional (3D) vertical NAND flash cell array architecture pose a critical reliability challenge due to the lower unselected word line (WL) pass bias (Vpass) window. In other words, the key contradiction of program disturbance is that the operational Vpass during the program’s performance cannot be too high or too low. For instance, the 3D NAND program’s operation string needs a lower Vpass bias to suppress unselected WL Vpass bias-induced Fowler–Nordheim tunneling (FN tunneling), but for the inhibited string, the unselected WL needs a higher Vpass bias to suppress selected WL program bias (Vpgm)-induced FN tunneling. In this paper, a systematical insight into the relationship between the channel potential and channel electron density is given. Based on this intensive investigation, we studied a novel channel preparation scheme using “Gate-induced drain leakage (GIDL) pre-charge”. Our methodology does not require the introduction of any new structures in 3D NAND, or changes in the operational Vpass bias. Instead, the potential on the unselected channel is enhanced by exploiting the holes generated by the GIDL operation effectively, leading to significantly suppressed program disturbance and a larger pass disturb window. To validate the effectiveness of the “GIDL pre-charge” method, TCAD simulation and real silicon data are used.

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“…Multiple V th states are created within a limited V th window between the erase (ERS) and the program (PGM) V th [ 12 , 13 ]. Then, if the V th window is widened, the errors in distinguishing V th states can be reduced by obtaining the margin of each V th state.…”

Section: Introductionmentioning

confidence: 99%

Optimal Energetic-Trap Distribution of Nano-Scaled Charge Trap Nitride for Wider Vth Window in 3D NAND Flash Using a Machine-Learning Method

et al. 2022

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A machine-learning (ML) technique was used to optimize the energetic-trap distributions of nano-scaled charge trap nitride (CTN) in 3D NAND Flash to widen the threshold voltage (Vth) window, which is crucial for NAND operation. The energetic-trap distribution is a critical material property of the CTN that affects the Vth window between the erase and program Vth. An artificial neural network (ANN) was used to model the relationship between the energetic-trap distributions as an input parameter and the Vth window as an output parameter. A well-trained ANN was used with the gradient-descent method to determine the specific inputs that maximize the outputs. The trap densities (NTD and NTA) and their standard deviations (σTD and σTA) were found to most strongly impact the Vth window. As they increased, the Vth window increased because of the availability of a larger number of trap sites. Finally, when the ML-optimized energetic-trap distributions were simulated, the Vth window increased by 49% compared with the experimental value under the same bias condition. Therefore, the developed ML technique can be applied to optimize cell transistor processes by determining the material properties of the CTN in 3D NAND Flash.

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Issues and Key Technologies for Next Generation 3D NAND

Cited by 5 publications

References 11 publications

Extraction of Nitride Trap Profile in 3-D NAND Flash Memory Using Intercell Program Pattern

Extraction of Nitride Trap Profile in 3-D NAND Flash Memory Using Intercell Program Pattern

A Novel Channel Preparation Scheme to Optimize Program Disturbance in Three-Dimensional NAND Flash Memory

Optimal Energetic-Trap Distribution of Nano-Scaled Charge Trap Nitride for Wider Vth Window in 3D NAND Flash Using a Machine-Learning Method

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