Jitter minimization in Digital Transmission using dual phase locked loops

Abstract

Timing jitter is a concern in high frequency timing circuits. Its presence can degrade system performance in many high-speed applications. In this paper, a new method for minimization of timing jitter due to phase locked loops is described. The timing jitter can be minimized using two phase locked loops connected in cascade, where the first one has Voltage Controlled crystal Oscillator (VCXO) to eliminate the input jitter and the second is a wide band phase locked loop. Usually, RMS jitter is used to describe jitter performance of the system and that can be analyzed. Simulation results for the measurement of jitter in both phase locked loop using MATLAB Simulink are presented. The methodology described is also applicable to other types of clock generator.Index Terms -key words-Jitter, oscillator noise, oscillator stability, phase jitter, phase locked loops, phase noise, voltage controlled oscillators lINTRODUCTION Phase Locked Loop (PLL) technology is used in wide range of applications including modem data communication, wireless communications, as well as computer related microprocessor, data bus, video and audio ICs. As the speed of microprocessors approach and exceed 5 GHz, and the serial data transmission rate approaches and exceeds 10 Gb/s, the difficulties and complexities of designing and manufacturing a PLL at these speeds become severe. An important problem in PLL design and manufacturing is to simulate, measure, and verify its loop response and noise processes in order to achieve goals of good time and frequency domain responses, as well as good noise and jitter performance. In this paper, we will introduce a novel methodology that is capable of simulating a PLL loop response and