Jitter reduction of a digital phase-locked loop

Yamashita, M.; Tsuji, T.; Nishimura, Takahiro; Murata, Masaki; Namekawa, T.

doi:10.1109/proc.1976.10396

Cited by 4 publications

(1 citation statement)

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“…That is, the loop can add o r substract only an integer-fold of d to o r from @,,, so that denoting that the residue of dividing I do1 by A is mod ( 1 A s seen above and in Eqs. (1) to (8), if the loop constants, such a s the division ratio K, N of RWF and L of AND filter a r e known, and the variance ui of input jitter distribution and the initial phase difference @o a r e known, all required constants for the state transition diagram in Fig. 5 a r e defined.…”

Section: Andate Transition Diagram Of the Loopmentioning

confidence: 99%

A digital phase‐locked loop with and filter

Kurita

Yokoyama

Mori

et al. 1980

Electron. Comm. Jpn. Pt. I

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In general, it is known that if the stationary characteristics of a PPL, phase‐locked loop, are improved, its transient response characteristics are deteriorated, while if the transient response characteristics are improved, its stationary characteristics are deteriorated. The DPLL, digital PLL, is not an exception in regards to the features. Here, we will realize a loop which is superior both in the effective phase error and the average transient response time compared with conventional DPLL with less deterioration of the average transient response time caused by improved effective phase error, due to inserting AND filter to the conventional binary quantized DPLL. The characteristics of the proposed loop are analyzed theoretically by use of the Markov chain and confirmed to be identical by computer simulation. These results prove that the proposed loop has better characteristics than the conventional ones.

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Section: Andate Transition Diagram Of the Loopmentioning

confidence: 99%