Jitter spectral extraction for multi-gigahertz signal

Ong, Chee-Kian; Hong, Dongwoo; Cheng, Kwang-Ting; Wang, L.-C.

doi:10.1109/aspdac.2004.1337584

Cited by 19 publications

(10 citation statements)

References 17 publications

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“…This estimation technique can derive the BER accurately by incorporating the receiver's specification with the transmitter's jitter spectral information. The spectral contents of jitter can be measured by the techniques proposed in [8,9,10]. By measuring the jitter transfer function of the CDR circuit, this technique also can estimate the BER without directly measuring it for jitter tolerance testing.…”

Section: Introductionmentioning

confidence: 99%

Bit Error Rate Estimation for Improving Jitter Testing of High-Speed Serial Links

Hong

Cheng

2006

2006 IEEE International Test Conference

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This paper describes a Bit Error Rate (BER) estimation technique for high-speed serial links, which utilizes the jitter spectral information extracted from the transmitted data and some key characteristics of the clock and data recovery (CDR) circuit in the receiver. In addition to improving the accuracy of BER prediction, the estimation technique can be used to accelerate the jitter tolerance test by eliminating the conventional BER measurement process. Experimental results comparing the estimated BER and the BERT-measured BER on a 2.5 Gbps commercial CDR circuit demonstrate the high accuracy of the proposed technique.

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Section: Introductionmentioning

confidence: 99%

Bit Error Rate Estimation for Improving Jitter Testing of High-Speed Serial Links

Hong

Cheng

2006

2006 IEEE International Test Conference

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“…In [3], an on-chip version of the technique is fabricated and verified. The technique in [6] utilizes onchip single-shot time measurement unit to measure the signal periods. Sample time estimation, period estimation, and FFT are then applied to the sequence of measured periods to derive the SJ amplitude and frequency.…”

Section: Introductionmentioning

confidence: 99%

A Random Jitter Extraction Technique in the Presence of Sinusoidal Jitter

Huang

2006

2006 15th Asian Test Symposium

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In this paper, a random jitter (RJ) extraction technique in the presence of sinusoidal jitter (SJ) is proposed for onchip jitter tolerance testing applications. First, the periodtracking technique [4] is utilized to derive the SJ frequency and amplitude information. Then, using the same designfor-test (DfT) circuitry, samples from the total jitter cumulative distribution function (CDF) are taken. From the SJ information and CDF samples, a binary search method is utilized to obtain the RJ sigma value. The features of the proposed technique include low delay line resolution requirement and high process variation tolerance. Simulation results are performed and shown to validate the proposed technique.

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“…To ensure accuracy, both methods depend on external reference clocks and external equipment. However, the jitter characteristics of a signal may not be necessarily sinusoidal [37]. Assuming the jitter characteristics of a signal with a double-delta PDF leads to inaccurate estimating DJ and RJ, as well as the performance of the system [36].…”

Section: Related Work On Transmitter Jitter Testingmentioning

confidence: 99%

“…The method reported in [37] , propose a spectral analysis scheme for extracting jitter without requiring an ideal external sampling clock.…”

Section: Related Work On Transmitter Jitter Testingmentioning

confidence: 99%

Oversampled multi-phase time-domain bit-error rate processing for transmitter testing

Najafi

Banville²,

Hafed³

et al. 2013

Analog Integr Circ Sig Process

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High speed serial interfaces (HSSI) are continually pushed toward operating at higher speed to meet the demand for higher bandwidth. As a result, the timing constraints for HSSI devices get tighter. Consequently, HSSI devices experience issues such as timing jitter and bit-errors. This thesis investigates techniques to speed up bit-error rate (BER) and jitter testing of HSSI devices.This work proposes an oversampling-based transmitter test scheme that accelerates transmitter jitter as well as eye diagram testing through the deployment of a multi-phase bit-error rate test circuit (BERT). The proposed scheme creates parallel BERT elements working in conjunction that are able to digitize the input signal jitter behavior in a multi-phase manner. The more phases we deploy the faster the test is completed.We aim to accurately extract the transmitter jitter in time domain and finish the whole transmitter test within tens of milliseconds. This exceeds the performance of [2], which by itself was an improvement from seconds to 100 ms.ii

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Jitter spectral extraction for multi-gigahertz signal

Cited by 19 publications

References 17 publications

Bit Error Rate Estimation for Improving Jitter Testing of High-Speed Serial Links

Bit Error Rate Estimation for Improving Jitter Testing of High-Speed Serial Links

A Random Jitter Extraction Technique in the Presence of Sinusoidal Jitter

Oversampled multi-phase time-domain bit-error rate processing for transmitter testing

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