Key factors to sustain the extension of a MHM-based integration scheme to medium and high porosity PECVD low-k materials

Abstract

Interconnect solutions for advanced technology nodes using PECVD techniques for low-k deposition require the use of porogen-based process with post deposition UV cure. By using two different UV cure lamps (A, B) in combination with different porogen loads, three different micro-porous low-k films are developed: Aurora ELK HM (k~2.5; porosity (P) ~25%), Aurora ELK A (k~2.3; P~34%) and Aurora ELK B (k~2.2; P~37%). Integrating these materials is complex and challenging. We discuss key factors that are instrumental to the extension of a metal hard mask (MHM)-based integration scheme to these 3 low-k films. Our findings: (I) for sub-100nm dimensions, patterning and low-k interactions affect the dynamic of organic residue formation and thereby impact electrical yield; (II) choosing the right ash, etch and clean sequence is mandatory to control plasma damage, profile, residues and corrosion on top of the MHM; (III) Cu reduction plasmas must be adjusted when porosity is increased to mitigate field damage.

Copper Metal for Semiconductor Interconnects

“…To minimize the damage on the porous low-k material, low-k material optimization and resist strip condition are chosen, and the process integration modification has been provided. The integration approach for dual damascene patterning is transformed to "metal hardmask" method from 32 nm technology node as shown in Figure 2 [27]. In the metal hardmask method, the resist strip damage on the porous low-k material can be minimized because the resist is stripped prior to the trench and via etching.…”

Process Technology for Copper Interconnects

“…Hence, the process integration and resist strip conditions must be chosen carefully to minimize etch damage [55][56][57][58][59]. Hence, the process integration and resist strip conditions must be chosen carefully to minimize etch damage [55][56][57][58][59].…”

“…These complicated methods are needed for patterning small features because the resist thickness must be reduced as feature size decreases to ensure an adequate process window for lithography [61]. However, there are a number of problems with the metal hardmask approach [56,57]. However, there are a number of problems with the metal hardmask approach [56,57].…”

Electrical Breakdown in Advanced Interconnect Dielectrics

“…Another form of surface damage is the presence of Cu residues on top of the LK/ULK surface, which can also further degrade the reliability margin against IMD breakdown [200]. Despite these difficulties, reasonably successful integration of SiCOH-based ULK BEOL has been demonstrated [205][206][207][208][209][210][211][212], even with BEOL stacks that include CoWP metal capping over Cu metallization [20,213,214]. Despite these difficulties, reasonably successful integration of SiCOH-based ULK BEOL has been demonstrated [205][206][207][208][209][210][211][212], even with BEOL stacks that include CoWP metal capping over Cu metallization [20,213,214].…”