Key process steps for high performance and reliable 3D Sequential Integration

Low-Temperature (≤500 °C) Complementary Schottky Source/Drain FinFETs for 3D Sequential Integration

“…The process flow of Schottky S/D FinFETs is summarized in Figure 1 a. SOI wafers measuring 200 mm with top Si of 40 nm and BOX of 145 nm were used as the starting materials to mimic the bonded substrate of top-tier devices. The replacement metal gate (RMG) process was adopted, and all process steps were set below the typical thermal budget of 550 °C for compatibility with 3D sequential integration [ 3 , 4 , 5 ]. According to the principle of Schottky S/D MOSFETs [ 18 ], the electrical property is primarily determined by the Schottky junction barrier between S/D and channel.…”

“…This technology can enhance circuit density and functionality without the requirement of further reduction in device dimensions. To maintain the integrity of what is below, namely the bottom devices, interconnections and bonding interface, the thermal budget for top-tier fabrication is required to be no more than 550 °C [ 3 , 4 , 5 ].…”

Recent progress in low-temperature-process monolithic three dimension technology

“…29,30) 1.2 Active layer transfer Active layer transfer is a simple way to prevent a potential high-temperature 3D stackable channel process during sequential stacking and obtain high-quality channels for manufacturing sequentially 3D stackable devices. [31][32][33][34][35][36][37] Batude and coworkers of CEA-Leti proposed their first 3D CMOS sequential integration in VLSI in 2009 using the SmartCut technique, which was originally designed to obtain high quality germanium-on-insulator (GOI) and silicon-on-insulator (SOI) wafer. 33,34) Subsequently, SiGe and III-V materials were also considered for monolithic stacking in various aspects, for example, InGaAs=Ge dual-channel CMOS inverters utilizing stacked 3D integration by Irisawa and coworkers of AIST 35,36) and 3D monolithic hybrid CMOS -InGaAs nFETs on SiGe-OI Fin pFETs by Deshpande et al of IBM.…”

“…[31][32][33][34][35][36][37] Batude and coworkers of CEA-Leti proposed their first 3D CMOS sequential integration in VLSI in 2009 using the SmartCut technique, which was originally designed to obtain high quality germanium-on-insulator (GOI) and silicon-on-insulator (SOI) wafer. 33,34) Subsequently, SiGe and III-V materials were also considered for monolithic stacking in various aspects, for example, InGaAs=Ge dual-channel CMOS inverters utilizing stacked 3D integration by Irisawa and coworkers of AIST 35,36) and 3D monolithic hybrid CMOS -InGaAs nFETs on SiGe-OI Fin pFETs by Deshpande et al of IBM. 37) Carbon nanotubes (CNTs) [38][39][40] and layered semiconductors (e.g., MoS 2 and WSe 2 ) [41][42][43] considered as candidates of future ultimately scaled nanodevice materials were proposed for monolithic 3D integration as well.…”