Kilo-NOC

Abstract

Today's chip-level multiprocessors (CMPs) feature up to a hundred discrete cores, and with increasing levels of integration, CMPs with hundreds of cores, cache tiles, and specialized accelerators are anticipated in the near future. In this paper, we propose and evaluate technologies to enable networks-on-chip (NOCs) to support a thousand connected components (Kilo-NOC) with high area and energy efficiency, good performance, and strong quality-of-service (QOS) guarantees. Our analysis shows that QOS support burdens the network with high area and energy costs. In response, we propose a new lightweight topology-aware QOS architecture that provides service guarantees for applications such as consolidated servers on CMPs and real-time SOCs. Unlike prior NOC quality-of-service proposals which require QOS support at every network node, our scheme restricts the extent of hardware support to portions of the die, reducing router complexity in the rest of the chip. We further improve network area-and energy-efficiency through a novel flow control mechanism that enables a single-network, low-cost elastic buffer implementation. Together, these techniques yield a heterogeneous Kilo-NOC architecture that consumes 45% less area and 29% less power than a state-of-the-art QOSenabled NOC without these features.

Providing multiple hard latency and throughput guarantees for packet switching networks on chip

“…The complex task of prioritizing packets to provide guaranteed QoS is pushed out to the source node, requiring global knowledge in each node to take concurrent communication into account. Preemptive Virtual Clock (PVC) [12], applied in the Kilo-NoC [26], is another scheme allowing different bandwidth guarantees per flow by utilizing priority scheduling. Compared to GSF it has a better bandwidth utilization and a lower area overhead due to reduced input buffer sizes.…”