KiloCore: A 32 nm 1000-processor array

Bohnenstiehl, Brent; Stillmaker, Aaron; Pimentel, Jon J.; Andreas, Timothy; Liu, Bin; Tran, Anh; Adeagbo, Emmanuel; Baas, Bevan M.

doi:10.1109/hotchips.2016.7936218

Cited by 13 publications

(7 citation statements)

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“…Manycore architectures that omit cache-coherency features fall into two main camps: message-passing [1,2,4,7] and PGAS [3,5,6]. In PGAS, cores communicate by performing remote loads and stores to local memories of other cores.…”

Section: Related Workmentioning

confidence: 99%

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General hardware multicasting for fine-grained message-passing architectures

Naylor

Moore

Thomas

et al. 2021

2021 29th Euromicro International Conference on Parallel, Distributed and Network-Based Processing (PDP)

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Manycore architectures are increasingly favouring message-passing or partitioned global address spaces (PGAS) over cache coherency for reasons of power efficiency and scalability. However, in the absence of cache coherency, there can be a lack of hardware support for one-to-many communication patterns, which are prevalent in some application domains. To address this, we present new hardware primitives for multicast communication in rack-scale manycore systems. These primitives guarantee delivery to both colocated and distributed destinations, and can capture large unstructured communication patterns precisely. As a result, reliable multicast transfers among any number of software tasks, connected in any topology, can be fully offloaded to hardware. We implement the new primitives in a research platform consisting of 50K RISC-V threads distributed over 48 FPGAs, and demonstrate significant performance benefits on a range of applications expressed using a high-level vertexcentric programming model.

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Section: Related Workmentioning

confidence: 99%

“…Instead, processors consisting of larger numbers of far simpler cores, communicating by messagepassing or PGAS, can achieve more performance from a single chip, and scale more easily to large numbers of chips. This is the premise behind a number of recently developed manycore designs [1,2,3,4,5,6,7].…”

Section: Introductionmentioning

confidence: 99%

General hardware multicasting for fine-grained message-passing architectures

Naylor

Moore

Thomas

et al. 2021

2021 29th Euromicro International Conference on Parallel, Distributed and Network-Based Processing (PDP)

View full text Add to dashboard Cite

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“…To demonstrate our many-core architectures, we utilize the Kilo-Core 32 nm chip [5,7] to execute three canonical Huffman decoder designs. Each of the 1000 programmable processors in the array occupies 0.055 mm 2 and contains 575,000 transistors.…”

Section: Implementations 31 Many-core Processor Array Hardwarementioning

confidence: 99%

Canonical Huffman Decoder on Fine-grain Many-core Processor Arrays

Sarangi

Baas

2021

Proceedings of the 26th Asia and South Pacific Design Automation Conference

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Canonical Huffman codecs have been used in a wide variety of platforms ranging from mobile devices to data centers which all demand high energy efficiency and high throughput. This work presents bit-parallel canonical Huffman decoder implementations on a fine-grain many-core array built using simple RISC-style programmable processors. We develop multiple energy-efficient and area-efficient decoder implementations and the results are compared with an Intel i7-4850HQ and a massively parallel GT 750M GPU executing the corpus benchmarks: Calgary, Canterbury, Artificial, and Large. The many-core implementations achieve a scaled throughput per chip area that is 324× and 2.7× greater on average than the i7 and GT 750M respectively. In addition, the many-core implementations yield a scaled energy efficiency (bytes decoded per energy) that is 24.1× and 4.6× greater than the i7 and GT 750M respectively. CCS CONCEPTS• Mathematics of computing → Coding theory; • Computer systems organization → Multiple instruction, multiple data.

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“…NVIDIA [2] has integrated 5.12K cores on a GPU chip. UC-Davis with IBM has integrated 1000 cores on a single chip [9]. However, communication is the major bottleneck to achieve high parallelism in systems with many compute nodes as communication costs much more time and energy than that of computation [6], [42], [51].…”

Section: Introductionmentioning

confidence: 99%

Reinforcement Learning Enabled Routing for High-Performance Networks-on-Chip

Reza

Le²

2021

2021 IEEE International Symposium on Circuits and Systems (ISCAS)

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Network-on-chip (NoC) has been the standard fabric for multi-core architectures. With the increase in cores in the multi-core architectures, the probability of congestion increases because of longer path among sources and destinations in the NoC and because of the presence of multiple applications in a chip. Congestion hampers system performance because of the delay in packet delivery, which in turn results in reduced effective utilization of resources and reduced throughout. Higher congestion also results in higher energy consumption in NoC as packets spend more time in the network. Reactive detection and/or a single fixed routing algorithm are not effective to prevent congestion from happening for different traffic patterns in NoC. Therefore, we propose reinforcement learning based proactive routing technique that selects the best routing algorithm from multiple available routing algorithms using NoC utilization and congestion information to improve communication performance. Simulation results demonstrate latency performance improvement while providing robust NoC performance for different NoC states and traffic demands.

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KiloCore: A 32 nm 1000-processor array

Cited by 13 publications

References 0 publications

General hardware multicasting for fine-grained message-passing architectures

General hardware multicasting for fine-grained message-passing architectures

Canonical Huffman Decoder on Fine-grain Many-core Processor Arrays

Reinforcement Learning Enabled Routing for High-Performance Networks-on-Chip

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