Kinetic Model of SiGe Selective Epitaxial Growth Using RPCVD Technique

Abstract

Recently, selective epitaxial growth (SEG) of B-doped SiGe layers has been used in recessed source/drain (S/D) of pMOSFETs. The uniaxial induced strain enhances the carrier mobility in the channel. In this work, a detailed model for SEG of SiGe has been developed to predict the growth rate and Ge content of layers in dichlorosilane(DCS)-based epitaxy using a reduced-pressure CVD reactor. The model considers each gas precursor contributions from the gas-phase and the surface. The gas flow and temperature distribution were simulated in the CVD reactor and the results were exerted as input parameters for Maxwell energy distribution. The diffusion of molecules from the gas boundaries was calculated by Fick's law and Langmuir isotherm theory (in non-equilibrium case) was applied to analyze the surface. The pattern dependency of the selective growth was also modeled through an interaction theory between different subdivisions of the chips. Overall, a good agreement between the kinetic model and the experimental data were obtained.

A Kinetic Model for Chemical-Vapor Deposition of Pure-Boron Layers from Diborane

“…Following ref. (15) for the solution of the diffusion problem in a semi-infinite system with a capturing boundary at y = 0, and using Fick's law gives [11] Because the active component is only consumed at y = 0 (over the susceptor), the average concentration at x = x 0 , ) ( 0 x C…”

“…In recent years, various theories have been proposed to describe the transport phenomena in CVD reactors (9)(10)(11). Most of these have modeled the epitaxial growth of Si and SiGe layers, and they can be divided into two main groups.…”

“…The second encompasses models that consider the surface reactions (e.g. 10,11). Since in CVD reactors the boundary layer is stationary or at most moving slowly, the input value of partial pressure of the reactants cannot be upheld throughout the chamber.…”

Optimization of Selective Growth of SiGe for Source/Drain in 14nm and Beyond Nodes FinFETs

“…This type of epitaxy suffers from a problem so-called pattern dependency which yields to different SiGe profiles across the transistor arrays. This behavior occurs when the density and size of the transistor vary in a chip [13][14][15][16][17][18][19]. The reason behind the pattern dependency of SEG is non-uniform consumption of reactant gas molecules when the exposed Si area varies over the chip.…”