Kinetic modeling of no-flow underfill cure and its relationship to solder wetting and voiding

Hurley, J.M.; Berfield, T.; Ye, S.; Johnson, Richard W.; Zhao, Renzhe; Tian, Guoyun

doi:10.1109/ectc.2002.1008196

Cited by 8 publications

(3 citation statements)

References 6 publications

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“…The source of void formation remained unidentified, and it was assumed that unidentified reactions caused bubble nucleation during the reflow process. Hurley et al used experimental techniques to suggest a combined model for void formation with solder melting, underfill curing, and underfill volatilization in order to explain the mechanism of voiding in a flip chip device [19]. They suggested the void formation was mainly due to explosive boiling of uncured low-molecular weight components due to molecular components' volatilizations during reflow process.…”

Section: Introductionmentioning

confidence: 99%

Void Formation Study of Flip Chip in Package Using No-Flow Underfill

Lee

Yim

Master

et al. 2008

IEEE Trans. Electron. Packag. Manufact.

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The advanced flip chip in package (FCIP) process using no-flow underfill material for high I/O density and fine-pitch interconnect applications presents challenges for an assembly process that must achieve high electrical interconnect yield and high reliability performance. With respect to high reliability, the voids formed in the underfill between solder bumps or inside the solder bumps during the no-flow underfill assembly process of FCIP devices have been typically considered one of the critical concerns affecting assembly yield and reliability performance. In this paper, the plausible causes of underfill void formation in FCIP using no-flow underfill were investigated through systematic experimentation with different types of test vehicles. For instance, the effects of process conditions, material properties, and chemical reaction between the solder bumps and no-flow underfill materials on the void formation behaviors were investigated in advanced FCIP assemblies. In this investigation, the chemical reaction between solder and underfill during the solder wetting and underfill cure process has been found to be one of the most significant factors for void formation in high I/O and fine-pitch FCIP assembly using no-flow underfill materials.

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Section: Introductionmentioning

confidence: 99%

Void Formation Study of Flip Chip in Package Using No-Flow Underfill

Lee

Yim

Master

et al. 2008

IEEE Trans. Electron. Packag. Manufact.

View full text Add to dashboard Cite

show abstract

“…Therefore, the void formation characterization found that the soak temperature has strong effect on the underfill voiding with the high I/O, fine-pitch flip chip on substrate. Indeed, the most significant effect on no-flow underfill voiding was reported as the chemical reaction between solder melting and underfill curing in the FCIP [13], [19]. The chemical reaction between solder melting and underfill curing is mainly induced by the fluxing agent.…”

Section: B Void Formation Characterizationmentioning

confidence: 99%

“…Many researchers have thoroughly identified the causes of void formation in flip chip assemblies. Mainly the source of void formation can classified into thermally induced voids [1], [11]- [18], and nonthermally induced voids [19]. Typically, a chip placement process or the geometry effect of a test vehicle's design can cause nonthermally induced voids.…”

mentioning

confidence: 99%

Near Void-Free Assembly Development of Flip Chip Using No-Flow Underfill

Yim

Master

et al. 2009

IEEE Trans. Electron. Packag. Manufact.

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The advanced flip-chip-in-package (FCIP) process technology, using no-flow underfill material for high I/O density (over 3000 I/O) and fine-pitch (down to 150 m) interconnect applications, presents challenges for flip chip processing because underfill void formation during reflow drives interconnect yield down and degrades reliability. In spite of such challenges, a high yield, reliable assembly process ( 99 99%) has been achieved using commercial no-flow underfill material with a high I/O, fine-pitch FCIP. This has been obtained using design of experiments with physical interpretation techniques. Statistical analysis determined what assembly conditions should be used in order to achieve robust interconnects without disrupting the FCIP interconnect structure. However, the resulting high yield process had the side effect of causing a large number of voids in the FCIP assemblies. Parametric studies were conducted to develop assembly process conditions that would minimize the number of voids in the FCIP induced by thermal effects. This work has resulted in a significant reduction in the number of underfill voids. This paper presents systematic studies into yield characterization, void formation characterization, and void reduction through the use of structured experimentation which was designed to improve assembly yield and to minimize the number of voids, respectively, in FCIP assemblies.

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