Kinetics of Buffer-Related R_ON-Increase in GaN-on-Silicon MIS-HEMTs

Impact of gate insulator on the dc and dynamic performance of AlGaN/GaN MIS-HEMTs

“…Slow trapping phenomena are analysed by means of drain current transients (DCTs). The device is kept in a trapping (or detrapping) bias condition for 1000 s; the drain current corresponding variation is monitored in knee voltage region (V GSI , V DSI ) with instantaneous measurements [11], in order not to influence the trapping (or detrapping) condition.…”

“…Previous results demonstrated the impact of the high drain bias and hot electrons, induced during off-state bias and semi-on-state bias respectively, on the dynamic on-resistance increase [8,10] and its correlation, during off-state condition, with the buffer vertical leakage current and the gate-drain length [7,11]. An analysis of MIS-HEMT slow trapping phenomena moreover demonstrated that significant trapping effects (e.g.…”

Analysis of off-state leakage mechanisms in GaN-based MIS-HEMTs: Experimental data and numerical simulation

“…In GaN-on-Si technologies, the existence of an inversion layer at p-Si=AlN interface [19], and the potentially high defectiveness of the III-nitrides transition and buffer layers can compromise the vertical insulation towards the substrate [20]. Substrate leakage current features an exponential dependence with respect to the drain voltage, and a thermal activation energy of 0.39 eV (Fig.…”

Technology and Reliability of Normally-Off GaN HEMTs with p-Type Gate

“…When the transistor is in the off-state (condition (1) in Figure 1), a high drain-source voltage is applied to the HEMT. The high resulting field ( Figure 2) may favor charge trapping mechanisms, including the filling/depletion of defects located in the C-doped buffer [6], the injection of electrons from the substrate [7], and surface trapping processes [8]. These mechanisms are typically fully recoverable.…”