Kyber Accelerator on FPGA Using Energy-Efficient LUT-Based Barrett Reduction

Kim, Da Won; Maulana, Dalta Imam; Jung, Wanyeong

doi:10.1109/isocc56007.2022.10031533

Cited by 3 publications

(1 citation statement)

References 8 publications

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“…Bit-Parallel NTT (BP-NTT) [6] architecture uses static random access memory (SRAM) and bit-parallel modular multiplication to improve their NTT process. Barret reduction is a popular modular algorithm for optimizing the butterfly unit [7]. Fritzman and Sepulveda [8] discuss possible side-channel attacks on NTT hardware implementation and propose a low-power design with a single-port RAM.…”

Section: Introductionmentioning

confidence: 99%

Efficient number theoretic transform accelerator for CRYSTALS-Kyber

Nguyen,

Anh Pham,

Nguyen

et al. 2024

IJEECS

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<p>The national institute of standards and technology (NIST) has presented its draft of the module-lattice-based key-encapsulation mechanism standard (MLBKEMS), choosing cryptographic suite for algebraic lattices (CRYSTALS)- Kyber as the base encryption. Existing hardware implementations of modern cryptography will need to process the new standard efficiently. The primary process in CRYSTALS-Kyber key-encapsulation mechanism (KEM) is the number theoretic transform (NTT), which requires heavy computing power. This paper contributes an efficient hardware accelerator for NTT and inverse NTT (INTT) by CRYSTAL-Kyber parameters. The proposed design utilizes the K-RED algorithm for reducing polynomial multiplication. It also incorporates the BrentKung method for efficient modular addition and subtraction operation with an address generator to control the sequences of computation. On the Xilinx Artix 7 field programmable gate array (FPGA), our design achieves 262 MHz clock speed, utilizing only 1405 LUTs.</p>

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Section: Introductionmentioning

confidence: 99%

Efficient number theoretic transform accelerator for CRYSTALS-Kyber

Nguyen,

Anh Pham,

Nguyen

et al. 2024

IJEECS

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Conceptual Review on Number Theoretic Transform and Comprehensive Review on Its Implementations

et al. 2023

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Hardware Acceleration for High-Volume Operations of CRYSTALS-Kyber and CRYSTALS-Dilithium

Carril,

Kardaris,

Ribes-GonzáLez

et al. 2024

ACM Trans. Reconfigurable Technol. Syst.

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Many high-demand digital services need to perform several cryptographic operations, such as key exchange or security credentialing, in a concise amount of time. In turn, the security of some of these cryptographic schemes is threatened by advances in quantum computing, as quantum computer could break their security in the near future. Post-Quantum Cryptography (PQC) is an emerging field that studies cryptographic algorithms that resist such attacks. The National Institute of Standards and Technology (NIST) has selected the CRYSTALS-Kyber Key Encapsulation Mechanism and the CRYSTALSDilithium Digital Signature algorithm as primary PQC standards. In this paper, we present FPGA-based hardware accelerators for high-volume operations of both schemes. We apply High-Level Synthesis (HLS) for hardware optimization, leveraging a batch processing approach to maximize the memory throughput, and applying custom HLS logic to specific algorithmic components. Using reconfigurable field-programmable gate arrays (FPGAs), we show that our hardware accelerators achieve speedups between 3x and 9x over software baseline implementations, even over ones leveraging CPU vector architectures. Furthermore, the methods used in this study can also be extended to the new CRYSTALS-based NIST FIPS drafts, ML-KEM and ML-DSA, with similar acceleration results.

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Kyber Accelerator on FPGA Using Energy-Efficient LUT-Based Barrett Reduction

Cited by 3 publications

References 8 publications

Efficient number theoretic transform accelerator for CRYSTALS-Kyber

Efficient number theoretic transform accelerator for CRYSTALS-Kyber

Conceptual Review on Number Theoretic Transform and Comprehensive Review on Its Implementations

Hardware Acceleration for High-Volume Operations of CRYSTALS-Kyber and CRYSTALS-Dilithium

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