Language-level persistency

Abstract

The commercial release of byte-addressable persistent memories, such as Intel/Micron 3D XPoint memory, is imminent. Ongoing research has sought mechanisms to allow programmers to implement recoverable data structures in these new main memories. Ensuring recoverability requires programmer control of the order of persistent stores; recent work proposes persistency models as an extension to memory consistency to specify such ordering. Prior work has considered persistency models at the abstraction of the instruction set architecture. Instead, we argue for extending the language-level memory model to provide guarantees on the order of persistent writes. We explore a taxonomy of guarantees a language-level persistency model might provide, considering both atomicity and ordering constraints on groups of persistent stores. Then, we propose and evaluate Acquire-Release Persistency (ARP), a language-level persistency model for C++11. We describe how to compile code written for ARP to a state-of-the-art ISA-level persistency model. We then consider enhancements to the ISA-level persistency model that can distinguish memory consistency constraints required for proper synchronization but unnecessary for correct recovery. With these optimizations, we show that ARP increases performance by up to 33.2% (19.8% avg.) over coding directly to the baseline ISA-level persistency model for a suite of persistent-write-intensive workloads. CCS CONCEPTS • Computer systems organization → Architectures; • Software and its engineering → Software notations and tools;

Persistency semantics of the Intel-x86 architecture

“…a write) visible to other threads, whilst the latter denotes the process of committing instruction effects durably to persistent memory. Existing persistency models [Gogte et al 2018;Izraelevitz et al 2016b;Kolli et al 2017;Pelley et al 2014;] can be categorised along two axes: (1) strict versus relaxed; (2) unbuffered versus buffered.…”

“…The existing literature on software persistency is more limited. Kolli et al [2017] propose acquire-release persistency (ARP), an analogue to release-acquire consistency in C/C++. Gogte et al [2018] propose synchronisation-free regions (regions delimited by synchronisation operations or system calls).…”

“…persistent memory) will eventually supplant volatile memory, allowing efficient access to persistent data [Intel 2014;ITRS 2011;Pelley et al 2014]. This has led to a surge in NVM research in recent years [Boehm and Chakrabarti 2016;Chakrabarti et al 2014;Chatzistergiou et al 2015;Coburn et al 2011;Gogte et al 2018;Izraelevitz et al 2016a;Kolli et al 2017Nawab et al 2017;Volos et al 2011;Wu and Reddy 2011;Zhao et al 2013;Zuriel et al 2019].…”

“…their permitted behaviours upon recovery) by prescribing the order in which writes are persisted to memory. Existing literature includes several proposals of persistency models varying in strength and performance [Condit et al 2009;Gogte et al 2018;Izraelevitz et al 2016b;Joshi et al 2015;Kolli et al 2017Kolli et al , 2016b]. However, none of these works explore the persistency semantics of the mainstream Intel-x86 architecture ].…”

Weak persistency semantics from the ground up: formalising the persistency semantics of ARMv8 and transactional models

“…persistent memory) will eventually supplant volatile memory, allowing for efficient access to persistent data [Intel 2014;ITRS 2011;Pelley et al 2014]. As such, the NVM literature has grown rapidly over the recent years [Boehm and Chakrabarti 2016;Chakrabarti et al 2014;Chatzistergiou et al 2015;Coburn et al 2011;Gogte et al 2018;Izraelevitz et al 2016a;Kolli et al 2017Nawab et al 2017;Volos et al 2011;Wu and Reddy 2011;Zhao et al 2013].…”