Language-level persistency

Abstract

The commercial release of byte-addressable persistent memories, such as Intel/Micron 3D XPoint memory, is imminent. Ongoing research has sought mechanisms to allow programmers to implement recoverable data structures in these new main memories. Ensuring recoverability requires programmer control of the order of persistent stores; recent work proposes persistency models as an extension to memory consistency to specify such ordering. Prior work has considered persistency models at the abstraction of the instruction set architecture. Instead, we argue for extending the language-level memory model to provide guarantees on the order of persistent writes. We explore a taxonomy of guarantees a language-level persistency model might provide, considering both atomicity and ordering constraints on groups of persistent stores. Then, we propose and evaluate Acquire-Release Persistency (ARP), a language-level persistency model for C++11. We describe how to compile code written for ARP to a state-of-the-art ISA-level persistency model. We then consider enhancements to the ISA-level persistency model that can distinguish memory consistency constraints required for proper synchronization but unnecessary for correct recovery. With these optimizations, we show that ARP increases performance by up to 33.2% (19.8% avg.) over coding directly to the baseline ISA-level persistency model for a suite of persistent-write-intensive workloads. CCS CONCEPTS • Computer systems organization → Architectures; • Software and its engineering → Software notations and tools;

Free atomics

“…We run parallel applications from the SPLASH-3 [47] (simmedium inputs), PARSEC 3.0 [9] (simmedium inputs) and a suite of writeintensive benchmarks [20,30]. We pinned the threads to the cores to prevent the scheduler from generating an unbalanced load.…”

“…Figure 1 quantifies that cost, split into cycles waiting to drain the SB (Drain_SB) and cycles waiting for the atomic RMW to commit (Atomic) as measured in our simulation infrastructure using gem5-20 [36] and running Splash-3 [47], Parsec-3 [8], and a modern suite of write-intensive benchmarks [20,30] (see Section 5.1 for detailed information). The average cost of atomic RMWs, dominated by Drain_SB cycles, is generally more than 100 cycles for Skylake (224-entry reorder buffer -ROB-) and increases for Icelake (352-entry ROB).…”

Ribbon

“…Many other efforts that use CLF to enable crash consistency provide solutions in PM-aware programming models [7,19], languagelevel persistency [18,29]. Our solution is generally applicable to most of the existing software interfaces as their building block relies on CLF.…”

Vorpal

“…Assuming the programmer used the persistency model correctly, this cut should be a state from which the program can recover its data. We chose a relatively relaxed persistency model called acquire-release persistency (ARP) [23] in order to demonstrate the flexibility of the Vorpal algorithms -with some work, Vorpal should support stricter persistency models as well.…”