LAP: Loop-Block Aware Inclusion Properties for Energy-Efficient Asymmetric Last Level Caches

Cheng, Hsiang-Yun; Zhao, Jishen; Sampson, Jack; Irwin, M.J.; Jaleel, Aamer; Lu, Yu; Xie, Yuan

doi:10.1109/isca.2016.19

Cited by 13 publications

(13 citation statements)

References 28 publications

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“…Dynamic LLC Bypassing can be a good solution for mitigating the long write latency of STT-RAM [21][22][23][24][25][26][27][28]. Wang et al [21] defined an interesting characteristic called LLCobstruction, which can occur by a write-intensive process, and used it for dynamic LLC bypassing.…”

Section: Related Workmentioning

confidence: 99%

“…In [22], an LLC congestion-aware bypassing technique is proposed to eliminate a large fraction of writes. Cheng et al [23] introduced the concept of loop-block and proposed a loop-block-aware replacement policy to keep the loop-block in the LLC. Ahn et al [24] defined dead write, which is the data written on LLC and not re-referenced during the lifetime of the corresponding cache block.…”

Section: Related Workmentioning

confidence: 99%

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Exploiting Data Compression for Adaptive Block Placement in Hybrid Caches

Kim

Nair

et al. 2022

Electronics

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STT-RAM (Spin-Transfer Torque Random Access Memory) appears to be a viable alternative to SRAM-based on-chip caches. Due to its high density and low leakage power, STT-RAM can be used to build massive capacity last-level caches (LLC). Unfortunately, STT-RAM has a much longer write latency and a much greater write energy than SRAM. Researchers developed hybrid caches made up of SRAM and STT-RAM regions to cope with these challenges. In order to store as many write-intensive blocks in the SRAM region as possible in hybrid caches, an intelligent block placement policy is essential. This paper proposes an adaptive block placement framework for hybrid caches that incorporates metadata embedding (ADAM). When a cache block is evicted from the LLC, ADAM embeds metadata (i.e., write intensity) into the block. Metadata embedded in the cache block are then extracted and used to determine the block’s write intensity when it is fetched from main memory. Our research demonstrates that ADAM can enhance performance by 26% (on average) when compared to a baseline block placement scheme.

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Section: Related Workmentioning

confidence: 99%

Section: Related Workmentioning

confidence: 99%

Exploiting Data Compression for Adaptive Block Placement in Hybrid Caches

Kim

Nair

et al. 2022

Electronics

View full text Add to dashboard Cite

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“…The relative magnetic direction of these layers determines whether the cell resistance is low or high. In other words, the magnetic direction of the free layer specifies the stored binary value of the cell [13]. Even though STT-RAM provides ultra-low leakage power, high density comparable with dynamic random-access memory (DRAM), read latency and read energy comparable with SRAM, it suffers from long write latency and high write energy.…”

Section: Structure Of Stt-rammentioning

confidence: 99%

Integer linear programming model for allocation and migration of data blocks in the STT‐RAM‐based hybrid caches

Khajekarimi

Jamshidi

Vafaei

2020

IET Computers & Digital Techniques

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Spin-transfer torque random access memory (STT-RAM) has emerged as an eminent choice for the larger on-chip caches due to high density, low static power consumption and scalability. However, this technology suffers from long latency and high energy consumption during a write operation. Hybrid caches alleviate these problems by incorporating a write-friendly memory technology such as static random access memory along with STT-RAM technology. The proper allocation of data blocks has a significant effect on both performance and energy consumption in the hybrid cache. In this study, the allocation and migration problem of data blocks in the hybrid cache is examined and then modelled using integer linear programming (ILP) formulations. The authors propose an ILP model with three different objective functions which include minimising access latency, minimising energy and minimising energy-delay product in the hybrid cache. Evaluations confirm that the proposed ILP model obtains better results in terms of energy consumption and performance compared to the existing hybrid cache architecture.

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“…Similarly, Cheng et al [22] proposed LAP, a technique which combines both non-inclusive and exclusive designs to manage the way the caches are handled in the LLCs. By using exclusive properties in the cache policy, the LAP is able to cache only the required data of the upper-level data in the LLC to reduce redundant writes.…”

Section: A Sram and Stt-ram Architecturesmentioning

confidence: 99%

A Survey of Low Power Design Techniques for Last Level Caches

Ofori-Attah

Wang

Agyeman

2018

Applied Reconfigurable Computing. Architectures, Tools, and Applications

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The end of Dennard scaling has shifted the focus of performance enhancement in technology to power budgeting techniques, specifically in the nano-meter domain because, leakage power depletes the total chip budget. Therefore, to meet the power budget, the number of resources per die could be limited. With this emerging factor, power consumption of on-chip components is detrimental to the future of transistor scaling. Fortunately, earlier research has identified the Last Level Cache (LLC) as one of the major power consuming element. Consequently, there have been several efforts towards reducing power consumption in LLCs. This paper presents a survey of recent contribution towards reducing power consumption in the LLC.

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LAP: Loop-Block Aware Inclusion Properties for Energy-Efficient Asymmetric Last Level Caches

Cited by 13 publications

References 28 publications

Exploiting Data Compression for Adaptive Block Placement in Hybrid Caches

Exploiting Data Compression for Adaptive Block Placement in Hybrid Caches

Integer linear programming model for allocation and migration of data blocks in the STT‐RAM‐based hybrid caches

A Survey of Low Power Design Techniques for Last Level Caches

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