Large Dispersive Interaction between a CMOS Double Quantum Dot and Microwave Photons

Ibberson, David J.; Lundberg, Theodor; Haigh, J. A.; Hutin, Louis; Bertrand, Benoît; Barraud, S.; Lee, Chang-Min; Stelmashenko, Nadia; Oakes, Giovanni A.; Cochrane, Laurence; Robinson, Jason W. A.; Vinet, M.; González-Zalba, M. Fernando; Ibberson, Lisa

doi:10.1103/prxquantum.2.020315

Cited by 39 publications

(27 citation statements)

References 59 publications

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“…Here we have introduced a new set of parameters a = λa, b = λb and t = t/λ, and the arbitrary scaling factor λ. We choose a possible scaling factor λ := 100 MHz such that the resulting optimal phyisical parameters fall into a regime that can be realised with near-term technology (see [108] for the possibility of reaching large chargecavity couplings). Note, however, that the optimal unitary dynamics can be mapped to any other regime, e.g., choosing λ := 200 MHz allows a faster generation of Bell pairs (t = 7.5 ns) but requires the fabrication of twice as large couplings (and all other dymanical parameters twice as large).…”

Section: Discussionmentioning

confidence: 99%

Multicore Quantum Computing

Jnane,

Undseth,

Cai

et al. 2022

Preprint

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Any architecture for practical quantum computing must be scalable. An attractive approach is to create multiple cores, computing regions of fixed size that are well-spaced but interlinked with communication channels. This exploded architecture can relax the demands associated with a single monolithic device: the complexity of control, cooling and power infrastructure as well as the difficulties of cross-talk suppression and near-perfect component yield. Here we explore interlinked multicore architectures through analytic and numerical modelling. While elements of our analysis are relevant to diverse platforms, our focus is on semiconductor electron spin systems in which numerous cores may exist on a single chip. We model shuttling and microwave-based interlinks and estimate the achievable fidelities, finding values that are encouraging but markedly inferior to intra-core operations. We therefore introduce optimsed entanglement purification to enable highfidelity communication, finding that 99.5% is a very realistic goal. We then assess the prospects for quantum advantage using such devices in the NISQ-era and beyond: we simulate recently proposed exponentially-powerful error mitigation schemes in the multicore environment and conclude that these techniques impressively suppress imperfections in both the inter-and intra-core operations.

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Section: Discussionmentioning

confidence: 99%

Multicore Quantum Computing

Jnane,

Undseth,

Cai

et al. 2022

Preprint

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“…2(b), is covered by the pair of split gates which are separated by a face-to-face distance S gg (≈ 30 nm) and enable local electrostatic control of the nanowire. At deep cryogenic temperatures, when positive voltages are applied to the gates, few-electron QDs form in the top-most corners of the device due to the corner effect [41][42][43], as shown in Fig. 2(b).…”

Section: Architecture Embodiment In Siliconmentioning

confidence: 99%

Compilation and scaling strategies for a silicon quantum processor with sparse two-dimensional connectivity

Crawford¹,

Cruise²,

Mertig³

et al. 2022

Preprint

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Inspired by the challenge of scaling up existing silicon quantum hardware, we investigate compilation strategies for sparsely-connected 2d qubit arrangements and propose a spin-qubit architecture with minimal compilation overhead. Our architecture is based on silicon nanowire split-gate transistors which can form finite 1d chains of spin-qubits and allow the execution of two-qubit operations such as Swap gates among neighbors. Adding to this, we describe a novel silicon junction which can couple up to four nanowires into 2d arrangements via spin shuttling and Swap operations. Given these hardware elements, we propose a modular sparse 2d spin-qubit architecture with unit cells consisting of diagonally-oriented squares with nanowires along the edges and junctions on the corners. We show that this architecture allows for compilation strategies which outperform the bestin-class compilation strategy for 1d chains, not only asymptotically, but also down to the minimal structure of a single square. The proposed architecture exhibits favorable scaling properties which allow for balancing the trade-off between compilation overhead and colocation of classical control electronics within each square by adjusting the length of the nanowires. An appealing feature of the proposed architecture is its manufacturability using complementary-metal-oxide-semiconductor (CMOS) fabrication processes. Finally, we note that our compilation strategies, while being inspired by spin-qubits, are equally valid for any other quantum processor with sparse 2d connectivity.

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“…A concrete milestone would be to reach a 10-MHz amplification bandwidth in combination with an input signal power handling capacity of about −120 dBm. A sub-GHz JPA meeting these specifications would boost the readout fidelities of nano-calorimeters tailored for the detection of fewmicrowave-photon energies [11], for example, and facilitate the development of single-shot readout of spin qubits [7], [12].…”

Section: Introductionmentioning

confidence: 99%

A Sub-GHz Impedance-Engineered Parametric Amplifier for the Readout of Sensors and Quantum Dots

Vesterinen

Simbierowicz

Jabdaraghi

et al. 2022

IEEE Trans. Appl. Supercond.

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In the work on superconducting parametric amplifiers, the frequency band below one gigahertz is calling for systematic improvements. Despite a prospect for ultralow added noise, bandwidth limitations have slowed down the integration of such amplifiers into sub-GHz experiments demanding fast (< 1 µs) readout speeds. Here, we study the impedance engineering of a flux-driven Josephson parametric amplifier (JPA) at 600 MHz. We propose, simulate and experimentally demonstrate a partially reconfigurable impedance transformer. The transformer enhances the JPA bandwidth to a state-ofthe-art value of 10 MHz at 20 dB gain. Our amplifier has immediate applications in the readout of cryogenic sensors and in the reflectometry of quantum dots for spin qubit quantum computing.

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Large Dispersive Interaction between a CMOS Double Quantum Dot and Microwave Photons

Cited by 39 publications

References 59 publications

Multicore Quantum Computing

Multicore Quantum Computing

Compilation and scaling strategies for a silicon quantum processor with sparse two-dimensional connectivity

A Sub-GHz Impedance-Engineered Parametric Amplifier for the Readout of Sensors and Quantum Dots

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