Laser Mapping of SRAM Sensitive Cells: A Way to Obtain Input Parameters for DASIE Calculation Code

Miller, F.; Buard, N.; Hubert, G.; Alestra, Stephane; Baudrillard, G.; Carrière, T.; Gaillard, R.; Palau, J.M.; Saigné, Frédéric; Fouillat, P.

doi:10.1109/tns.2006.880938

Cited by 20 publications

(6 citation statements)

References 18 publications

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“…Previous works on laser testing in Virtex-II SRAM-based FPGAs have discussed the capability of using localized photoelectric stimulation to analyze soft errors in the configuration memory bits of CLBs and BRAMs [10], to deduce the configuration memory bit organization and thus identify where configuration memory bits are laid out on the silicon surface [11], and to analyze the occurrence of multiple bit upsets (MBUs) in the configuration memory cells [12]. In [13], soft error in the POR of the Virtex-II is investigated.…”

Section: Spels Laser Facility and Related Workmentioning

confidence: 99%

Laser Testing Methodology for Diagnosing Diverse Soft Errors in a Nanoscale SRAM-Based FPGA

Kastensmidt

Tambara

Bobrovsky

et al. 2014

IEEE Trans. Nucl. Sci.

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In this paper, we propose a method that combines dedicated test designs, readback and bitstream comparisons to investigate soft errors in a nanoscale SRAM-based FPGA under photoelectric stimulation. Static test is performed to analyze the SEU dependency to voltage supply. Static cross-section and threshold energy are presented. Dynamic test is accomplished by using a set of designs in order to diagnose errors from SET in the logic clock tree, SEU in embedded soft-core processor and in the reconfigurable ICAP interface. A picosecond laser is used in the experiments.Index Terms-Laser testing, soft errors, SRAM-based FPGAs.

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Section: Spels Laser Facility and Related Workmentioning

confidence: 99%

Laser Testing Methodology for Diagnosing Diverse Soft Errors in a Nanoscale SRAM-Based FPGA

Kastensmidt

Tambara

Bobrovsky

et al. 2014

IEEE Trans. Nucl. Sci.

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“…With an appropriate wavelength, thanks to photoelectric effect, laser can locally generates charges in silicon as ionizing particles can do with coulombian interactions. Several published works described the tool and its application to study radiation effects on various components [7][8]. In order to avoid opacity problems due to die metallization, laser pulses are performed from the backside of the component with the beam focused on the frontside, where transistors are located.…”

Section: Atest Setupmentioning

confidence: 99%

Novel DRAM mitigation technique

Bougerol

Miller

Buard

2009

2009 15th IEEE International on-Line Testing Symposium

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This paper describes a novel patented radiation mitigation technique for DRAM cell memories. Because of their non-symmetrical structure, only one state is sensitive to radiations. This particular property is used to detect and correct upsets. Several fault-tolerant architectures are proposed, which are able to detect and correct all SEU/ MBU in a word, whatever its length. Overhead in term of additional memory cells is lower than other classical mitigation techniques.

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“…Sensitivity mapping technology is a significant branch of SEE laser testing. There are plenty of studies related to this area, e.g., 2-D mapping technique [8][9][10] and 3-D mapping technique [11,12]. However, most previous research is achieved with the region of interest (ROI) size in sub-millimeter scale and few of work focuses on the ROI with the size in about one micron scale which is even smaller than the spot size of the laser beam.…”

Section: Introductionmentioning

confidence: 99%

Developing a Universal Mirror–mirror Laser Mapping System for Single Event Effect Research

Belev

Tian

et al. 2020

Applied Sciences

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Research on single event effects (SEEs) is significant to the design and manufacture of modern electronic devices. By applying two photon absorption (TPA) ultra-fast pulsed lasers, extra electron-hole pairs (EHPs) are generated in a desired location on a chip, simulating the process that could occur in the circuit by energetic particles. In this study, a SEE sensitivity mapping system is described which uses this method to generate real-time sensitivity maps for various electronic devices. The system hardware includes an attenuator to control the energy, a Pockels cell as a fast-optical switcher and a mirror–mirror module to project the laser beam into a certain location. The system software developed for this application controls the laser system, automatically generates sensitivity maps, communicates with the testing devices and logs the SEE results. The two main features of this laser mapping system are: high scanning velocity for large area scanning (about 1 × 1 mm) and high spatial resolution for small area scanning (about 1 × 1 μm). To verify this mapping system, sensitivity maps were generated for static random access memory (SRAM) built with 65 nm technology and for commercial operational amplifiers (op-amps). The achieved sensitivity maps were compared with circuitry analysis and laser testing results, confirming this mapping system to be effective.

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Laser Mapping of SRAM Sensitive Cells: A Way to Obtain Input Parameters for DASIE Calculation Code

Cited by 20 publications

References 18 publications

Laser Testing Methodology for Diagnosing Diverse Soft Errors in a Nanoscale SRAM-Based FPGA

Laser Testing Methodology for Diagnosing Diverse Soft Errors in a Nanoscale SRAM-Based FPGA

Novel DRAM mitigation technique

Developing a Universal Mirror–mirror Laser Mapping System for Single Event Effect Research

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