Latency, Power and Performance Trade-Offs in Network-on-Chips by Link Microarchitecture Exploration

Talwar, Basavaraj; Kulkarni, Shailesh; Amrutur, Bharadwaj

doi:10.1109/vlsi.design.2009.55

Cited by 6 publications

(2 citation statements)

References 8 publications

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“…NoC consumes a significant portion of total chip power in multicore systems. Some recent researches in a low power network on chip design [26]- [28] architectures are validated to be 10% -36%. Therefore, necessities of latency and power-aware NoC lead to a serious issue in designing low power multicore systems.…”

Section: Related Workmentioning

confidence: 99%

FSM Based DFS Link for Network on Chip

Sakthivel¹,

Veeraraghavan²,

Arunraja³

et al. 2016

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As low power consumption is the main design issue involved in a network on chip (NoC), researchers are concentrating more on both algorithms and architectural approaches. The conventional Dynamic Frequency Scaling (DFS) and history based Frequency Scaling (HDFS) algorithms are utilized to process the energy constrained data traffic. However, these conventional algorithms achieve higher energy efficiencies, and they result in performance degradation due to the auxiliary latency between clock domains. In this paper, we present a variable power optimization interface for NoC using a Finite State Machine (FSM) approach to attain better performance improvement. The parameters are estimated using 45 nm TSMC CMOS technology. In comparison with DFS system, the evaluation results show that FSM-DFS link achieves 81.55% dynamic power savings on the links in the on-chip network, and 37.5% leakage power savings of the link. Also, this proposed work is evaluated for various performance parameters and compared with conventional work. The simulation results are superior to conventional work. Keywords Network-on-Chip (NoC), Dynamic Frequency Scaling (DFS), Finite State Machines (FSM)How to cite this paper: Sakthivel, E., Malathi, V., Arunraja, M. and Perumalvignesh, G. (2016) FSM Based DFS Link for Network on Chip. Circuits and Systems, 7, 1734-1750. http://dx.doi.org/10.4236/cs.2016.78150 E. Sakthivel et al. achieve peak performance of 1.0TFLOPS at 1 V, while dissipating 98 w [3].In [4], the Tile 64 processor design considerations such as arbitration, topology and length of physical links, width of physical links, buffer allocation, switching techniques, routing algorithms, and levels of service are addressed in the NoC core. This architectural challenge through "tiled" architecture can be connected by scalable and energy-efficient architecture.In general, the NoC architecture provides performance degradation by means of more scalability and high power consumption [5]. To achieve lower power consumption and a high operating speed, designers prefer the Dynamic Voltage and Frequency Scaling algorithm (DVFS) [6]. To avoid this complication, History based Dynamic Frequency Scaling (H-DFS) is introduced by Lee et al. [7]. In [8], Dynamic Voltage Scaling algorithm (DVS) implemented in a scalable architecture is developed by external circuit combinations of system configurations. The existing low power algorithms are used to reduce power consumption by adjusting the power mode of the links to match the traffic flows. These algorithms fail to act on sudden traffic changes. To overcome this issue, a novel application-driven approach for predicting traffic described in [9]. Here, a novel data structure called Application Traffic Prediction Table (ATPT) is used to record the core's outgoing messages (traffic) and the DFS policy is applied to the link. Conventional traffic generation is a novel structural design template that yields a complicated system level design [9]. In modern research, reducing the data access latency and energy consum...

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Section: Related Workmentioning

confidence: 99%

FSM Based DFS Link for Network on Chip

Sakthivel¹,

Veeraraghavan²,

Arunraja³

et al. 2016

View full text Add to dashboard Cite

show abstract

“…Talwar et al [32] present a study on NoC power, latency and throughput trade-offs. They vary micro architectural and circuit level parameters and use as support a NoC exploration framework capable of topology generation and comparison, using parameterized models of routers and links described in SystemC.…”

Section: Related Workmentioning

confidence: 99%