Layout Analysis And Automatic Test Point Selection For Fast Prototype Debug Using E-beam Or Laser-beam Testsystems

Abstract

This paper introduces a novel aRRroach for mauuing netn'mes to layout elements without using -layout-versus-;chimatic tools.Using this technique, a program has been developed that analyzes layouts, computes an observability degree for electron or laser beam testing, detects unobservable nets, and automatically selects probing points for chip-internal measurement. Shortened execution times and applicability to incomplete layout data are the main advantages over layoutversus-schematic based techniques. 17.3.1 IEEE 1992 CUSTOM INTEGRATED CIRCUITS CONFERENCE0-7803-0246-XI92 $3.00 0 1992 IEEE