Layout-oriented simulation of non-destructive single event effects in CMOS IC blocks

2010 27th International Conference on Microelectronics Proceedings

Stabile

et al. 2010

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Abstract-This paper presents the design of three static RAM cells, designed to be radiation hard. The memory cells are designed with three different approaches and layout styles. Three memory arrays, each of them made with a different cell, were designed and simulated to optimize the transistor sizes. The layout of the cells has been drawn, and parasitic elements were extracted to analyze their impact on circuit performance. Simulation results demonstrate that the three cells are functional in all worst case corners. The sensitivity of each cell to single events has been estimated using a fault injection technique. A silicon prototype employing the first cell has been fabricated and characterized.

“…Fault injection has been performed using FISAR, a dedicated tool that accounts for circuit layout [6]. Fault injection simulation results confirm a good level of radiation hardness.…”

Section: Simulation and Measurement Resultsmentioning

confidence: 92%

Design of rad-hard SRAM cells: A comparative study

Benigni

2010 27th International Conference on Microelectronics Proceedings

Stabile

et al. 2010

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“…The Fault Injection Simulation and Analysis for Radiation hardening (FISAR) tool has been used to validate the SEE robustness of blocks at layout level [4].…”

Section: Simulation Resultsmentioning

confidence: 99%

Double-redundant design methodology to improve radiation hardness in pixel detector readout ICs

Frontini

2015 IEEE International Conference on Electronics, Circuits, and Systems (ICECS)

Shojaii

et al. 2015

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This paper proposes a new design method to enhance the radiation hardness of circuits for the next generation of pixel detectors in High Energy Physics experiments. The approach is based on Radiation Hardness By Design methodology to mitigate Single Event Effects. In particle detectors, front-end electronics opeates in an environment characterized by a high dose of radiation. We propose a set of digital cells specifically designed to tolerate a high level of radiation (up to 1 Grad). The cells have been designed in 65 nm CMOS technology. Simulation results show the complete functionality up to 1 Grad of total dose of radiation. The first prototype chip has been designed and submitted for fabrication under the Istituto Nazionale di Fisica Nucleare (INFN) CHIPIX65 project.

“…We use the FISAR model presented in [3]. FISAR simulates the interaction between radiation and ICs at circuit level.…”

Section: Layout-oriented Simulationmentioning

confidence: 99%

Improvement of radiation tolerance in CMOS ICs through layout-oriented simulation

Bozzola

Fronting

2016 5th International Conference on Modern Circuits and Systems Technologies (MOCAST)

et al. 2016

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This paper proposes a methodology to design radiation-hardened ICs, suitable for space applications and highenergy physics experiments. The miniaturization of ICs has brought an increase of circuit logic errors due to radiation, also at ground level. The increased complexity of IC design due to technology scaling requires new tools to design rad-hard circuits.In this paper, we propose a design tool that employs a layoutoriented simulation approach to identify the sensitive IC area and provide data about the effects due to radiation.The simulation tool is implemented in Cadence LayoutGXL. The proposed approach will help to have a more efficient IC design reducing design time and costs related to the need of fabricating prototypes to be characterized under radiation to test their hardness.