Layout Technique for Single-Event Transient Mitigation via Pulse Quenching

Atkinson, N. M.; Witulski, A.F.; Holman, W.T.; Ahlbin, J. R.; Bhuva, B. L.; Massengill, L.W.

doi:10.1109/tns.2010.2097278

Cited by 88 publications

(42 citation statements)

References 11 publications

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“…Such layout design promotes charge sharing between nodes O and P, thereby suppressing SET pulse at Node O [2]. Minimum space between Node O and the two copies of Node P is applied to optimize area and charge sharing efficiency.…”

Section: Seu Simulations On Dynamic Logic Usingmentioning

confidence: 99%

Single Event Resilient Dynamic Logic Designs

Wang

Chen

et al. 2014

J Electron Test

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Dynamic logic families are commonly used in high speed applications, but they are susceptible to single event errors. This paper presents and evaluates three techniques of hardening dynamic logic-layout manipulation using charge sharing, addition of a feedback capacitor across the static inverter, and dual-rail domino logic with differential keepers. The layout-based design has better single event tolerance by sharing charge between NFET devices of the dynamic and static inverters; the design with a feedback capacitor makes the keeper more effective in recovering the hit node because of the increased propagation delay; the differential-keeper structure shows superior SET performance because the hit node could recover through the restoring path in the case of charge loss. These proposed designs along with the reference traditional keeper-based design were fabricated in a 130 nm technology node as shift register chains and then irradiated by heavy ion particles. Experimental results verified the mechanisms and effectiveness of these proposed designs.

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Section: Seu Simulations On Dynamic Logic Usingmentioning

confidence: 99%

Single Event Resilient Dynamic Logic Designs

Wang

Chen

et al. 2014

J Electron Test

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“…The combinational benchmark circuits for this study were chosen from the ISCAS85 suite and synthesized using a digital cell library for 90-nm bulk CMOS technology (Atkinson et al, 2011). The library contains 1034 cells that implement basic (e.g., NAND, NOR) and complex (e.g., AND-OR-INV, XOR) logic.…”

Section: Covering-based Reliability-aware Synthesismentioning

confidence: 99%

“…The actual transient shape will be defined by: (1) the particle type and energy, (2) the transistor size of the driver, (3) the load capacitance, and (4) the layout strategy. The pulse width and drain area values for each cell used in this study were calculated using TCAD and Accuro simulations and presented in (Atkinson et al, 2011). In (Atkinson et al, 2011), the drain area of each cell was identified to be most sensitive to ion strikes.…”

Section: Covering-based Reliability-aware Synthesismentioning

confidence: 99%

Impact of Logic Synthesis on Soft Error Rate of Digital Integrated Circuits

Limbrick

2012

2012 IEEE Computer Society Annual Symposium on VLSI

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“…At layout-level, guard rings and guard bands are usually used to sink excess charge away to reduce the produced SET pulse width [2,3]. A layout hardening technique presented by Atkinson et al [4] exploits the pulse quenching effect to limit the pulse origination. At circuit-level, the usual approach is to increase the device size [5,6].…”

Section: Introductionmentioning

confidence: 99%

A DMR logic for mitigating the SET induced soft errors in combinational circuits

Zhang

Yang

et al. 2016

IEICE Electron. Express

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In this paper, a novel dual module redundancy (DMR) logic circuit structure is proposed to harden the standard cells in the large combinational circuits. Three-dimensional TCAD simulation results present that this hardening structure can ultimately eliminate the SET pulse. Based on this DMR logic circuit structure and the layout placement adjustment technique, the partial hardening approach is used to harden the large combination circuits.

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Layout Technique for Single-Event Transient Mitigation via Pulse Quenching

Cited by 88 publications

References 11 publications

Single Event Resilient Dynamic Logic Designs

Single Event Resilient Dynamic Logic Designs

Impact of Logic Synthesis on Soft Error Rate of Digital Integrated Circuits

A DMR logic for mitigating the SET induced soft errors in combinational circuits

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