LDMOS Capacitance Analysis versus Gate and Drain Biases, Based on Comparison between TCAD Simulations and Measurements

Frre, S.F.; Rhayem, J.; Adawe, H.O.; Gillon, Renaud; Tack, M.; Walton, A.J.

doi:10.1109/essderc.2001.195240

Cited by 9 publications

(4 citation statements)

References 2 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Due to its advantages in performance, cost, reliability, and power capability, laterally diffused MOS (LDMOS) transistor technology has played a predominant role in the power amplifier applications [2]. Because the device capacitances influence the input, output, and feedback capacitances, which are important in the dynamic operation, and have large impact on device high-frequency performance, the capacitance characterization and modeling of LDMOS transistors have been studied widely [3]- [7]. As compared to the conventional MOSFET, a nonuniform doping channel and a drift region in LDMOS result in the unusual behavior in capacitances [8], [9].…”

mentioning

confidence: 99%

Temperature-Dependent Capacitance Characteristics of RF LDMOS Transistors With Different Layout Structures

Chen

Huang

et al. 2008

IEEE Electron Device Lett.

View full text Add to dashboard Cite

In this letter, the capacitance characteristics of RF LDMOS transistors with different temperatures and layout structures were studied. In a conventional fishbone structure, the peaks in capacitances decrease with increasing temperature. For the ring structure, two peaks in a capacitance-voltage curve have been observed at high drain voltages due to the additional corner effect. In addition, peaks in gate-to-source/body capacitance decrease and peaks in gate-to-drain capacitance increase with increasing temperature at high drain voltages. By analyzing the effects of temperature on threshold voltage, quasi-saturation current, and drift depletion capacitance, the variations of capacitances with temperature were investigated.

show abstract

mentioning

confidence: 99%

Temperature-Dependent Capacitance Characteristics of RF LDMOS Transistors With Different Layout Structures

Chen

Huang

et al. 2008

IEEE Electron Device Lett.

View full text Add to dashboard Cite

show abstract

“…A simple lateral shift of the C gs curve, without stretchout, indicates that there were no interface traps generated during the SHS for L = 50 lm. The C gd and C gs characteristics after SHS are very similar to the characteristics of a high voltage lateral double-diffused MOSFET (LDMOSFET), which has a laterally non-uniform doped channel [21][22][23]. Frere et al showed that the peak in C gd originates from the lateral non-uniform doping of the channel [21].…”

Section: Methodsmentioning

confidence: 81%

“…The C gd and C gs characteristics after SHS are very similar to the characteristics of a high voltage lateral double-diffused MOSFET (LDMOSFET), which has a laterally non-uniform doped channel [21][22][23]. Frere et al showed that the peak in C gd originates from the lateral non-uniform doping of the channel [21]. Analogously, the peak in C gd of a-Si:H TFT after the SHS can be explained by the non-uniform V t profile created by the V D -BTS stress.…”

Section: Methodsmentioning

confidence: 82%

Capacitance–voltage characteristics and device simulation of bias temperature stressed a-Si:H TFTs

Tang

Wie

2010

Solid-State Electronics

View full text Add to dashboard Cite

“…Many modeling investigations have been done till now. [6][7][8][9][10][11][12][13][14][15] However, we should pay attention on substrate bias effect of RESURF of LDMOS, as well.…”

Section: Introductionmentioning

confidence: 99%

Modeling of Reduced Surface Field Laterally Diffused Metal Oxide Semiconductor for Accurate Prediction of Junction Condition on Device Characteristics

Saito

Tanaka

Hayashi

et al. 2011

Jpn. J. Appl. Phys.

View full text Add to dashboard Cite

In this paper, an accurate model of resistive drift region in laterally diffused metal oxide semiconductor (LDMOS) is presented. We have improved the dynamically varying depletion width model at the drift/substrate junction, by considering both the drain and substrate bias effects. The both bias condition causes the resistance modification of the high resistive drift region for the reduced-surface-field structure (RESURF). In addition, new expansion-effect model is developed by considering the substrate bias effect. The developed models have been implemented into Hiroshima University starc insulated gate field effect transistor model for high voltage (HiSIM-HV) and it is proved that the models reproduce measured direct current (DC) characteristics for the wide variety of the substrate bias variation.

show abstract

LDMOS Capacitance Analysis versus Gate and Drain Biases, Based on Comparison between TCAD Simulations and Measurements

Cited by 9 publications

References 2 publications

Temperature-Dependent Capacitance Characteristics of RF LDMOS Transistors With Different Layout Structures

Temperature-Dependent Capacitance Characteristics of RF LDMOS Transistors With Different Layout Structures

Capacitance–voltage characteristics and device simulation of bias temperature stressed a-Si:H TFTs

Modeling of Reduced Surface Field Laterally Diffused Metal Oxide Semiconductor for Accurate Prediction of Junction Condition on Device Characteristics

Contact Info

Product

Resources

About