Leakage-and crosstalk-aware bus encoding for total power reduction

Abstract

Power consumption, particularly runtime leakage, in long on-chip buses has grown to an unacceptable portion of the total power budget due to heavy buffer insertion to combat RC delays. In this paper, we propose a new bus encoding algorithm and circuit scheme for on-chip buses that eliminates capacitive crosstalk while simultaneously reducing total power. We introduce a new buffer design approach with selective use of high threshold voltage transistors and couple this buffer design with a novel bus encoding scheme. The proposed encoding scheme significantly reduces total power by 26% and runtime leakage power by 42% while also eliminating capacitive crosstalk. In addition, the proposed encoding is specifically optimized to reduce the complexity of the encoding logic, allowing for a significant reduction in overhead which has not been considered in previous bus encoding work.

Network-on-Chip

“…Ghoneima and Ismail (2004), Kim et al (2000), and Zhang et al (2002) proposed another LPC scheme that reduces both self-transitions and coupling transitions by conditionally inverting the bus based on a metric that accounts for both the transitions at the price of increased complexity. While the above-mentioned works describe the methods of eliminating cross talk and/or reducing dynamic power, D0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 D0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 D1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 D1 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 D2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 D2 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 D3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 D3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 (Binary Sequence) (Gray Sequence) Deogun et al (2004) proposed an encoding scheme that also tackles the rising runtime leakage power levels in such buses along with cross talk and dynamic power. They introduced a new buffer design approach with selective use of high-threshold voltage transistors and coupled this buffer design with a novel bus encoding scheme.…”

Single-ended Coding Techniques for Off-chip Interconnects to Commodity Memory

“…Therefore, a significant number of external memory accesses will always remain. Memory compression [7][8][9][10][11] and coding [12][13][14][15][16][17][18][19][20][21][22][23][24][25] are well-known techniques to further reduce the energy consumption of the processor-memory interconnect and the external memory. However, memory compression techniques are best suited for instructions, not data, which leaves coding as the primary technique for reducing energy consumption on the interconnect for data transfers.…”

“…. coding techniques are almost all context-dependent, double-ended codes that require a codec (coder/decoder) on both ends of the interconnect [12][13][14][15][16][17][18][19][20][21][22][23][24]. Context-dependent codes use a one-to-many mapping in which the codeword is chosen based upon both the current and previous data values to cross the interconnect.…”

A low power SoC bus with low-leakage and low-swing technique

“…The inverter is widely used as hand, based on MTCMOS circuit topology, a bus encoding repeater in global bus architecture. The number and length of scheme considering leakage and crosstalk on global bus global bus lines which are necessary to communicate reduces total the power consumption [2]. between different modules in a SoC design have increased While the reviousl mentioned works reduce leakage significantly.…”

“…into reducing leakage power using MTCMOS. In the Sleep signal keeps flowu during the low swing mode, and Duplicated Skewed Bus (DSB) scheme [2], the repeaters are the signal swing is limited to an intermediate voltage level. skewed by the alternating use of high threshold (HVT) and low threshold (LVT) devices in the pull-up and pull-down A.…”