The CPM captures rising and falling edge delay on alternating Soraya G'iasi Tuyet Nguyn,NrmaJams,ichaclock cycles. The core CPM is 90x36pm2 and the nest CPM is 90x48gtm2 in 65nm SOI. There are 24 CPMs distributed across the IBM, Austin TX microprocessor ( Fig. 22.1.2): 8 in each core and 8 in the nest.Because of the time-to-digital nature of the output, its sensitivity Scaling has caused an inreas inpresvaron andithsnsi to multiple variables, and its distribution across the microprocestivity of cycle tile to workload and envlronemental conditions, sor, the CPM measures local power-supply droop, clock instability, making it difficult to predict the cycle tilme of lmicroprocessors. prcs vaitin NBIaderyaigefcs n eprtr , , , 1 , ,^.,~~~~~p rocess variation, NBTI and early aging effects, and temperature Cycle time is determined by the required performance with an in addition to timing; although, it is not always possible to sepaadded timing margin determined by the acceptable yield. After rate these effects. manufacture, microprocessors are binned into performance categories to account for process variation, but because of the influ- Figure 22.1.3 shows the measured delay versus voltage on nomience of the workload on cycle time, there is a danger of losing per-nal parts for the core CPM paths. The paths are normalized to formance with overly conservative timing margins. A critical-path demonstrate the different slopes of each delay path. There is some monitor (CPM) that measures critical-path delay and the effects of divergence in the pass-gate and wire delay paths from the MOS noise and localized VDD droops on timing is designed as part of the paths at the edges of the operating range. The small variation in POWER6 TM microprocessor. The CPM also measures across-chip POERMmirprocess or.riationt TealCe wealsou mea sacosm s-chi the wire-delay path demonstrates that for even large percentages process varIation anh rnd detectseartifm. u of wire delay, the MOS delay variation dominates the path delay. Figure 22.1.4 shows the average maximum frequency of the , microprocessor versus the measured bit position of the adder path the microprouessor,smanym difere timingy pathns my be criticeal, for the CPMs in core 0 at each voltage. The curve is generated byThe CPM uses a small number of delay paths with different delay running a heavy workload and increasing the frequency until failversus process, voltage, and temperature (DvPVT) curves to synure. If the CPM exactly tracks the critical path, the bit position at thesize the critical paths. It is a time-to-digital converter that uses failure should not change. There is an average of three bits of rise the system clock as the reference signal for conversion. The CPM, in the bit position as voltage rises, indicating the adder path does shown in Fig. 22.1.1, is composed of an edge-launching latch, not exactly match the critical path. None of the paths exactly delay-synthesis block, edge detector, data-analysis block, and contrack the critical path, but because the output is a the...

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Power consumption, particularly runtime leakage, in long on-chip buses has grown to an unacceptable portion of the total power budget due to heavy buffer insertion to combat RC delays. In this paper, we propose a new bus encoding algorithm and circuit scheme for on-chip buses that eliminates capacitive crosstalk while simultaneously reducing total power. We introduce a new buffer design approach with selective use of high threshold voltage transistors and couple this buffer design with a novel bus encoding scheme. The proposed encoding scheme significantly reduces total power by 26% and runtime leakage power by 42% while also eliminating capacitive crosstalk. In addition, the proposed encoding is specifically optimized to reduce the complexity of the encoding logic, allowing for a significant reduction in overhead which has not been considered in previous bus encoding work.

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