Adaptive MTCMOS for Dynamic Leakage and Frequency Control Using Variable Footer Strength

Deogun, Harmander S.; Sylvester, Dennis; Rao, Rajeev R.; Nowka, K.

doi:10.1109/socc.2005.1554483

Cited by 12 publications

(12 citation statements)

References 10 publications

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“…This is a constraint usually assumed by standard power gating approaches neglecting the effect of NBTI [6], [8]- [10], [15]. The obtained values of the ST equivalent aspect ratios S = (W/L) eq are: S b02 = 102; S N OT = 35.…”

Section: Analysis Of Nbti Impact On Sleep Transistorsmentioning

confidence: 94%

“…In standard power gating approaches [8]- [10], [15] high V th header STs are designed (sized) in order to achieve the desired trade-off in terms of IR drop and leakage power, without considering NBTI degradation. Therefore they identify an expected leakage power consumption as a target, which remains constant for the whole circuit lifetime.…”

Section: Background and Motivationmentioning

confidence: 99%

“…As a result, since STs are on the critical path, their degradation will reduce circuit performance and lifetime, thus causing long-term reliability issues [18]. While standard power gating approaches [8]- [10], [15] ignore the detrimental effect of NBTI on STs, a few countermeasures have been proposed to tackle NBTI effect on power-gated circuits [6], [18]. They mainly rely on ST network oversizing and adaptive body bias [6], [11], which allow designers to extend circuit lifetime and increase its long-term reliability at the cost of more area and increased design complexity.…”

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

NBTI and leakage aware sleep transistor design for reliable and energy efficient power gating

Rossi

Tenentes

Khursheed

et al. 2015

2015 20th IEEE European Test Symposium (ETS)

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Abstract-In this paper we show that power gating techniques become more effective during their lifetime, since the aging of sleep transistors (STs) due to negative bias temperature instability (NBTI) drastically reduces leakage power. Based on this property, we propose an NBTI and leakage aware ST design method for reliable and energy efficient power gating. Through SPICE simulations, we show lifetime extension up to 19.9x and average leakage power reduction up to 14.4% compared to standard STs design approach without additional area overhead. Finally, when a maximum 10-year lifetime target is considered, we show that the proposed method allows multiple beneficial options compared to a standard STs design method: either to improve circuit operating frequency up to 9.53% or to reduce ST area overhead up to 18.4%.

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Section: Analysis Of Nbti Impact On Sleep Transistorsmentioning

confidence: 94%

Section: Background and Motivationmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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NBTI and leakage aware sleep transistor design for reliable and energy efficient power gating

Rossi

Tenentes

Khursheed

et al. 2015

2015 20th IEEE European Test Symposium (ETS)

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“…This is a constraint usually adopted by standard power gating approaches neglecting the effect of NBTI [1], [8], [12]- [14]. The obtained values of the ST equivalent aspect ratios S ST eq = (W/L) eq are S ST eq (b02) = 110andS ST eq (N OT ) = 38, which represent approximately 23.1% and 12.7% of the area of the respective power gated circuit.…”

Section: A Simulation Set-upmentioning

confidence: 99%

“…Standard power gating approaches, as those presented in [1], [12]- [14], have so far ignored the detrimental effects of NBTI on header STs. They rely on the identification of IR drop, static power and ST switch efficiency (defined as the ratio between on and off currents [1]) constraints at time zero (t0), neglecting their variation over time due to NBTI aging.…”

Section: Introductionmentioning

confidence: 99%

Reliable Power Gating With NBTI Aging Benefits

Rossi

Tenentes

Yang

et al. 2016

IEEE Trans. VLSI Syst.

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Power-Gating for Leakage Control and Beyond

Calimera¹,

Macii²,

Macii³

et al. 2014

Circuit Design for Reliability

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The need of reliable nanometric integrated circuits is driving the EDA community to develop new automated design techniques in which power consumption and variability are central objectives of the optimization flow.Although several Design-for-Low-Power and Design-for-Variability options are already available in modern EDA suites, the contrasting nature of the two metrics makes their integration extremely challenging. Most of the approaches used to compensate and/or mitigate circuit variability (e.g., Dynamic Voltage Scaling and Adaptive Body Biasing) are, in fact, intrinsically power inefficient, as they exploit the concept of redundancy, which is known to originate power overhead.In this work, we introduce possible solutions for concurrent leakage minimization and variability compensation. More specifically, we propose Power-Gating as a mean for simultaneously controlling static power consumption and mitigating the effects induced by two of the most insidious sources of variability, namely, Process Variations (PV) due to uncertainties in the manufacturing and Transistor Aging due to Negative Bias Temperature Instability (NBTI).We show that power-gating, when implemented through the insertion of dedicated switches (called sleep transistors), has a double effect: On one hand, when sleep transistors are enhanced with tunable features, it acts as a natural supplyvoltage regulator, which implements a control knob for PV compensation; on the other hand, during the idle periods, it makes the circuits immune to NBTI-induced aging.We describe optimization techniques for the integration of a new concept of power-gating into modern sub-45 nm design flows, that is, Variation-Aware PowerGating. The experimental results we have obtained are extremely promising, since they show 100 % timing yield under the presence of PV and circuit lifetime extension of more than 5 in the presence of NBTI.

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Adaptive MTCMOS for Dynamic Leakage and Frequency Control Using Variable Footer Strength

Cited by 12 publications

References 10 publications

NBTI and leakage aware sleep transistor design for reliable and energy efficient power gating

NBTI and leakage aware sleep transistor design for reliable and energy efficient power gating

Reliable Power Gating With NBTI Aging Benefits

Power-Gating for Leakage Control and Beyond

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