Bus encoding for total power reduction using a leakage-aware buffer configuration

Rao, Rajeev R.; Deogun, Harmander S.; Blaauw, David; Sylvester, Dennis

doi:10.1109/tvlsi.2005.862718

Cited by 11 publications

(4 citation statements)

References 11 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Studies on the bus encoding schemes (for example, differential coding, gray coding, bus invert coding and the like) have been carried out to reduce bus power consumption [7][8][9][10][11][12][13]. The bus encoding schemes encode data values in every bus cycle to reduce the toggling frequency of a signal.…”

Section: Related Workmentioning

confidence: 99%

A Bus Data Compression Method on a Phase-Based On-Chip Bus

Lee¹

2012

JSTS:Journal of Semiconductor Technology and Science

View full text Add to dashboard Cite

Abstract-This paper provides a method for compression transmission of on-chip bus data. As the data traffic on on-chip buses is rapidly increasing with enlarged video resolutions, many video processor chips suffer from a lack of bus bandwidth and their IP cores have to wait for a longer time to get a bus grant. In multimedia data such as images and video, the adjacent data signals very often have little or no difference between them. Taking advantage of this point, this paper develops a simple bus data compression method to improve the chip performance and presents its hardware implementation. The method is applied to a Video Codec -1 (VC-1) decoder chip and reduces the processing time of one macro-block by 13.6% and 10.3% for SD and HD videos, respectively Index Terms-System-on-chip, on-chip bus, multimedia processor, VC-1 codec, video processor

show abstract

Section: Related Workmentioning

confidence: 99%

A Bus Data Compression Method on a Phase-Based On-Chip Bus

Lee¹

2012

JSTS:Journal of Semiconductor Technology and Science

View full text Add to dashboard Cite

show abstract

“…There have been many techniques used to reduce the activity factor on a multi-bit bus, that is, a parallel bus [14]- [20]. However, they are not applicable to serial interconnects since the principle of increasing the activity factor in serial communications is different from that in parallel communications as presented in the previous section.…”

Section: Related Workmentioning

confidence: 99%

On-Chip Bus Serialization Method for Low-Power Communications

Lee¹

2010

ETRI J

View full text Add to dashboard Cite

One of the critical issues in on‐chip serial communications is increased power consumption. In general, serial communications tend to dissipate more energy than parallel communications due to bit multiplexing. This paper proposes a low‐power bus serialization method. This encodes bus signals prior to serialization so that they are converted into signals that do not greatly increase in transition frequency when serialized. It significantly reduces the frequency by making the best use of word‐to‐word and bit‐by‐bit correlations presented in original parallel signals. The method is applied to the revision of an MPEG‐4 processor, and the simulation results show that the proposed method surpasses the existing one. In addition, it is cost‐effective when implemented as a hardware circuit since its algorithm is very simple.

show abstract

“…Additional ones exist for minimizing coupled switchings on lines [29], [37], [38], reducing transitions on lines [5], minimizing dynamic [39], static [6], peak [36] and leakage power [7]. Existing codes for crosstalk impact minimization like the Dual Rail (DR) and the Modified Dual Rail (MDR) codes in [24], [25] require more than 100% wire overhead.…”

Section: Introductionmentioning

confidence: 99%

A Data Capturing Method for Buses on Chip

Skoufis

Karmarkar

Tragoudas

et al. 2010

IEEE Trans. Circuits Syst. I

View full text Add to dashboard Cite

In this paper, a new data reading technique for a bus of lines is proposed for fast operation. The proposed method utilizes multiple reference voltages available within a line's receiving logic and the initial conditions of wires in order to determine early and accurately the transmitted data of the current cycle. The presented technique does not require repeater insertion for reasonably long lines and it can significantly accelerate signal propagation. Experimental results are given in the 65 nm CMOS process for interconnects of various lengths.

show abstract

Bus encoding for total power reduction using a leakage-aware buffer configuration

Cited by 11 publications

References 11 publications

A Bus Data Compression Method on a Phase-Based On-Chip Bus

A Bus Data Compression Method on a Phase-Based On-Chip Bus

On-Chip Bus Serialization Method for Low-Power Communications

A Data Capturing Method for Buses on Chip

Contact Info

Product

Resources

About