On-Chip Bus Serialization Method for Low-Power Communications

Lee, Jae-Sung

doi:10.4218/etrij.10.0109.0447

Cited by 12 publications

(5 citation statements)

References 5 publications

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“…In this paper, we proposed a lighting energy management system by using PC's power save mode as an occupancy sensing method. Although various energy management technologies have been developed in a chip and hardware level, we focused on an application level management to reduce the lighting energy management [10]- [13]. We described the correspondence between the lights and the PC's and explained the process mechanism.…”

Section: Discussionmentioning

confidence: 99%

Lighting Energy Management System Based on PC’s Power Save Mode

Han

Jeong

Lee

2012

AMM

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Lighting energy shares a large portion of building energy. Although lighting control system is deployed in the building, it has limited effects on reducing lighting energy use without the help of occupancy sensors. We use PC’s power save mode as an occupancy sensor in office buildings that are not equipped with occupancy sensors. When each PC goes to power save mode, it means that there is no one in that area, that is, no occupancy. If we make mapping relation between the lights and the PC’s, we can figure out when the light should be turned on and off from the state of PC’s power save mode. This scheme can contribute to reduction of lighting energy use in buildings that has lighting control system but has no occupancy sensors. The estimated results show the positive effect on reduction of the lighting energy use.

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Section: Discussionmentioning

confidence: 99%

Lighting Energy Management System Based on PC’s Power Save Mode

Han

Jeong

Lee

2012

AMM

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“…Bo decoding structures are placed at the ne before the serializer contrary to one on link CDBI [6] and SC [8] encoders operating on has also been implemented and mapped library. A comparison of area and powe illustrated in Fig 3.It can be observed that p (TSC) ensures minimum overhead in p (exception only in the case of BI encoder).…”

Section: B Logic Designmentioning

confidence: 99%

“…[8], [9] and [11] deal with reduction of switching activity in serial links (caused due to serialisation of parallel data). A few encoding techniques have been defined to take into consideration the contribution of crosscoupled capacitance [6], [12].…”

Section: Introductionmentioning

confidence: 99%

A Novel Encoding Scheme for Low Power in Network on Chip Links

Sarma

Lakshminarayanan

Chavali

2012

2012 25th International Conference on VLSI Design

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Dynamic power dissipation in interconnects is a major contributor to power consumption in Network on Chips (NoCs). This is mainly due to two factors, self switching activity of the particular link and coupling switching activity among adjacent links. Two novel techniques are proposed to reduce power consumption due to switching transition and crosstalk. First technique reorders the data in such a way that switching transition is brought down. In the second technique, it is ensured that power consumption due to cross coupling activity is reduced. An end to end encoding scheme facilitating two stage coding to reduce power consumption in wormhole routed network on chip is designed using the proposed power reduction techniques. Encoder and Decoder exhibiting the proposed scheme have been described in RTL level in Verilog HDL, synthesized and mapped into UMC180 nm technology library. It has been observed that the proposed technique (TSC) offers an average reduction in dynamic power consumption of 17.34%. Proposed scheme was compared with existing techniques and observations concluded that there was not much degradation in area, speed and static power dissipation. Power reduction when subjected to different kinds of data streams was analyzed and results indicate that proposed scheme offers uniform power reduction irrespective of the nature of data stream unlike the existing techniques.

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“…This means that double the wire costs are needed in asynchronous global signaling, and an increase in the number of wires among blocks can lead to a deterioration in design complexity and power consumption for an on-chip global interconnect. The bus serialization method [6] is one of solutions for this overhead.…”

Section: Introductionmentioning

confidence: 99%

Asynchronous 2-Phase Protocol Based on Ternary Encoding for On-Chip Interconnect

Oh¹

2011

ETRI J

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Level‐encoded dual‐rail (LEDR) has been widely used in on‐chip asynchronous interconnects supporting a 2‐phase handshake protocol. However, it inevitably requires 2N wires for N‐bit data transfers. Encoder and decoder circuits that perform an asynchronous 2‐phase handshake protocol with only N wires for N‐bit data transfers are presented for on‐chip global interconnects. Their fundamentals are based on a ternary encoding scheme using current‐mode multiple valued logics. Using 0.25 μm CMOS technologies, the maximum reduction ratio of the proposed circuits, compared with LEDR in terms of power‐delay product, was measured as 39.5% at a wire length of 10 mm and data rate of 100 MHz.

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On-Chip Bus Serialization Method for Low-Power Communications

Cited by 12 publications

References 5 publications

Lighting Energy Management System Based on PC’s Power Save Mode

Lighting Energy Management System Based on PC’s Power Save Mode

A Novel Encoding Scheme for Low Power in Network on Chip Links

Asynchronous 2-Phase Protocol Based on Ternary Encoding for On-Chip Interconnect

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