Asynchronous 2-Phase Protocol Based on Ternary Encoding for On-Chip Interconnect

Abstract

Level‐encoded dual‐rail (LEDR) has been widely used in on‐chip asynchronous interconnects supporting a 2‐phase handshake protocol. However, it inevitably requires 2N wires for N‐bit data transfers. Encoder and decoder circuits that perform an asynchronous 2‐phase handshake protocol with only N wires for N‐bit data transfers are presented for on‐chip global interconnects. Their fundamentals are based on a ternary encoding scheme using current‐mode multiple valued logics. Using 0.25 μm CMOS technologies, the maximum reduction ratio of the proposed circuits, compared with LEDR in terms of power‐delay product, was measured as 39.5% at a wire length of 10 mm and data rate of 100 MHz.

Wire Optimization and Delay Reduction for High-Performance on-Chip Interconnection in GALS Systems

“…In general, current‐mode multi‐valued logic circuits that use a current to express multiple values are preferred over voltage‐mode multi‐valued logic circuits that express multiple values using voltage levels because the noise margin characteristic of the voltage‐mode circuits is very unstable owing to the supply power, which is gradually decreased during operation. Thus, the methods applied in and through use current‐mode multi‐valued logic as a DI transmission mechanism. In fact, unlike voltage‐mode based circuits, a DI transmission based on current‐mode multi‐valued logic does not use a repeater or pipeline register to improve the data throughput, and is thus more advantageous in terms of cost and power efficiency compared to an interconnect employing voltage‐mode circuits.…”

“…To address this issue, the authors have devised a ternary encoding scheme for a two‐phase asynchronous protocol . The devised scheme uses current‐mode circuits to present multiple‐value signals in a single wire, and as a result, reduces the number of wires as much as four‐phase protocols.…”

Low Latency Synchronization Scheme Using Prediction and Avoidance of Synchronization Failure in Heterochronous Clock Domains

“…A complete data transfer should wait about one or two more clock cycles at each transfer through serialized two flip-flops, and the next data transfer cannot start before the previous data transfer is completed [10,14]. To prevent overheads caused by synchronizing with a two-flop synchronizer for all data bits on wide data paths, an asynchronous handshake protocol bundled with such data paths is typically used [12,15]. A speculative synchronizer [16] and a parallel flop synchronizer [17] to alleviate the inherent latency have been presented, but they have failed to perfectly eliminate the latency.…”