Wire Optimization and Delay Reduction for High-Performance on-Chip Interconnection in GALS Systems

Abstract

To address the wire complexity problem in largescale globally asynchronous, locally synchronous systems, a current-mode ternary encoding scheme was devised for a two-phase asynchronous protocol. However, for data transmission through a very long wire, few studies have been conducted on reducing the long propagation delay in current-mode circuits. Hence, this paper proposes a current steering logic (CSL) that is able to minimize the long delay for the devised current-mode ternary encoding scheme. The CSL creates pulse signals that charge or discharge the output signal in advance for a short period of time, and as a result, helps prevent a slack in the current signals. The encoder and decoder circuits employing the CSL are implemented using 0.25-lm CMOS technology. The results of an HSPICE simulation show that the normal and optimal mode operations of the CSL achieve a delay reduction of 11.8% and 28.1%, respectively, when compared to the original scheme for a 10-mm wire. They also reduce the power-delay product by 9.6% and 22.5%, respectively, at a data rate of 100 Mb/s for the same wire length.

Signal integrity analysis of system interconnection module of high‐density server supporting serial RapidIO

“…To decrease the crosstalk in a PCB board, the signals are placed 3W times away from the adjacent signal trace or are placed close to the power layer . In a system‐on‐a‐chip (SoC), the current steering logic was also proposed to reduce the propagation delay of the signals without broadening the metal width to be used to avoid capacitive crosstalk during high‐speed signaling . In addition, several studies on reducing the crosstalk in PCB boards have been conducted.…”