2005
DOI: 10.1109/mcas.2005.1550165
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Leakage sources and possible solutions in nanometer CMOS technologies

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Cited by 49 publications
(14 citation statements)
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“…Figure 11. DIBL vs V th [16] On the contrary, in the grooved nMOSFET simulated in this paper, the grooved structure nearly keeps the same threshold voltage for the simulated channel lengths for 90nm, 70nm and 50nm at 3nm, 4nm, and 5nm gate oxide thickness. The threshold voltage even increases as the channel length is reduced [17].…”
Section: Controlling V Th Roll-off and Diblmentioning
confidence: 70%
See 1 more Smart Citation
“…Figure 11. DIBL vs V th [16] On the contrary, in the grooved nMOSFET simulated in this paper, the grooved structure nearly keeps the same threshold voltage for the simulated channel lengths for 90nm, 70nm and 50nm at 3nm, 4nm, and 5nm gate oxide thickness. The threshold voltage even increases as the channel length is reduced [17].…”
Section: Controlling V Th Roll-off and Diblmentioning
confidence: 70%
“…Figure. 10. Barrier height lowering due to channel length reduction and drain voltage increase in a MOSFET [15] Drain-Induced Barrier Lowering (DIBL) effect for a short channel transistor in short channel transistors, in case of deep sub-micron and nanometer technologies, the depletion regions of the source and drain junctions causes some parts of the channel to be already depleted under the gate which, in turn, lowers the value of the threshold voltage needed for conduction to occur as in Fig 10. As a result of DIBL, threshold voltage is reduced with shorter channel lengths as shown in fig.11 and, consequently, the subthreshold leakage current is increased [16]. Figure 11.…”
Section: Controlling V Th Roll-off and Diblmentioning
confidence: 95%
“…It is the current flowing into the gate of the transistor also called the tunneling current. With current process technology parameters, gate leakage has increased to more than double the subthreshold current and will continue to increase at a much higher rate mandating the use of highk materials other than silicon dioxide to enable the use of thicker oxide thicknesses [10]. Control of gate-leakage current is paramount in low-power CMOS circuit design.…”
Section: Gate-leakage Currentmentioning
confidence: 99%
“…Promising results have been reported on the development of low-standby-power CMOS technology using HfO 2 gate dielectric. Transistors with gate length down to 55 nm, HfO 2 gate dielectric with electrical oxide thickness down to 15Å, and off-state leakage current of 25 pA/μm were demonstrated in [10]. As a result, there is immense interest in alternative gate dielectrics with higher relative permittivities.…”
Section: High-k Dielectrics To Combat Gate Tunneling Currentsmentioning
confidence: 99%
“…Moreover, this low data utilization also indicates a serious waste in the hardware area of SR memory, which is proportional to the static power. The static power is not a less important issue especially in the deep sub micron fabrication technology [6]. The SR data utilization rate simulated based on our previous work of H.264/AVC fast ME [2] is less than 30% for CIF videos with (SRH, SRV)=(32, 16), and even less than 15% for D1 videos with (SRH, SRv)=(64, 32).…”
Section: Introductionmentioning
confidence: 99%