A general self-aligned fabrication scheme is reported here for a diverse class of electronic devices based on van der Waals materials and heterojunctions. In particular, self-alignment enables the fabrication of source-gated transistors in monolayer MoS2 with near-ideal current saturation characteristics and channel lengths down to 135 nm. Furthermore, self-alignment of van der Waals p-n heterojunction diodes achieves complete electrostatic control of both the p-type and n-type constituent semiconductors in a dual-gated geometry, resulting in gate-tunable mean and variance of anti-ambipolar Gaussian characteristics. Through finite-element device simulations, the operating principles of source-gated transistors and dual-gated anti-ambipolar devices are elucidated, thus providing design rules for additional devices that employ self-aligned geometries.
2For example, the versatility of this scheme is demonstrated via contact-doped MoS2 homojunction diodes and mixed-dimensional heterojunctions based on organic semiconductors. The scalability of this approach is also shown by fabricating self-aligned short-channel transistors with subdiffraction channel lengths in the range of 150 nm to 800 nm using photolithography on large-area MoS2 films grown by chemical vapor deposition. Overall, this self-aligned fabrication method represents an important step towards the scalable integration of van der Waals heterojunction devices into more sophisticated circuits and systems.
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3Parallel self-aligned fabrication methods in modern silicon-based microelectronics have enabled sub-lithographic registration between processing steps, ultimately facilitating substantial advances in circuit complexity over the past few decades. 1 In contrast, while two-dimensional (2D) materials have shown significant potential for digital and analog electronics due to their high mobilities, ultrathin geometry, and broad range of permutations in van der Waals heterojunctions (vdWHs), 2-9 2D material devices have not yet exploited parallel self-aligned fabrication to achieve both short channels and large area fabrication. Thus far, short-channel 2D material transistors and vdWHs have been achieved using serial processing methods such as electron-beam lithography or mechanical placement on nanotube or nanowire gates. 5,10,11 Similarly, the relative alignment of different layers in vdWHs has been inhibited by the diffraction-limited resolution of transfer and alignment methods. Here, we overcome these limitations by introducing a self-aligned processing methodology that enables the fabrication of 2D material transistors with channel lengths below 150 nm with minimal short-channel effects and improved current saturation, as demonstrated with monolayer MoS2. These self-aligned transistors show the highest output resistance at the lowest channel length reported for a 2D material, which is of interest for high-frequency current amplifiers and mixers. In vdWHs based on black phosphorus (BP) and MoS2, this self-aligned approach allows dual-gate ...